Renesas IDT Tsi574 Manuals

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Renesas IDT Tsi574 User Manual

Renesas IDT Tsi574 User Manual (514 pages)

Serial RapidIO Switch

Brand: Renesas | Category: Switch | Size: 3 MB

Table of Contents

Table of Contents
3
About this Document
17
Scope
17
Document Conventions
17
Revision History
18
Functional Overview
21
Overview
21
Figure 1: Block Diagram
22
Figure 2: Processor Farm Mezzanine Diagram
22
Features
23
Figure 3: Switch Carrier Blade Diagram
23
Serial Rapidio Interface
26
Features
26
Transaction Flow Overview
26
Maintenance Requests
27
Control Symbols
27
Multicast Engine
27
Multicast Operation
27
Features
27
Serial Rapidio Electrical Interface
28
Figure 4: Tsi574 MAC Block Diagram
29
Internal Switching Fabric (ISF)
30
Internal Register Bus (AHB)
30
I 2 C Interface
30
JTAG Interface
32
Serial Rapidio Interface
35
Overview
35
Features
35
Transaction Flow Overview
36
Maintenance Requests
36
Control Symbols
36
Transaction Flow
37
Lookup Tables
37
Filling the Lookup Tables
38
Figure 5: LUT Mode of Operation
39
LUT Modes
40
Flat Mode
40
Figure 6: Flat Mode Routing
41
Figure 7: Flat Mode Routing Example
42
Figure 8: Flat Mode LUT Configuration Example
43
Hierarchical Mode
45
Figure 9: Hierarchical Mode
46
Figure 10: Hierarchical Mode Routing Example
47
Mixed Mode of Operation
49
Lookup Table Parity
49
Lookup Table Error Summary
50
Table 1: Error Summary
50
Lookup Table Entry States
51
Table 2: Lookup Table States
51
Maintenance Packets
53
Table 3: Examples of Maintenance Packets with Hop Count = 0 and Associated Tsi574 Responses
53
Multicast Event Control Symbols
55
MCS Reception
55
Generating an MCS
56
Restrictions
56
Reset Control Symbol Processing
57
Data Integrity Checking
57
Packet Data Integrity Checking
57
Control Symbol Data Integrity Checking
57
Error Management
57
Software Assisted Error Recovery
58
Hot Insertion and Hot Extraction
59
Hot Insertion
60
Hot Extraction
61
Hot Extraction System Notification
62
Loss of Lane Synchronization
62
Figure 11: LOLS Silent Period
63
Dead Link Timer
64
Lane Sync Timer
64
Serial Rapidio Electrical Interface
65
Overview
65
Figure 12: Tsi574 MAC Block Diagram
66
Port Numbering
67
Port Configuration
67
Port Aggregation: 1X and 4X Modes
67
Figure 13: Port Configuration
67
Table 4: Tsi574 Port Numbering
67
1X + 1X Configuration
68
Configuration
69
Clocking
69
Changing the Clock Speed
70
Table 5: Reference Clock Frequency and Supported Serial Rapidio Data Rates
70
Changing the Clock Speed through I
71
Port Power down
71
Default Configurations on Power down
72
Special Conditions for Port 0 Power down
72
Power-Down Options
73
Configuration and Operation through Power-Down
73
Table 6: Serial Port Power-Down Procedure
73
Port Lanes
74
Lane Synchronization and Alignment
74
Lane Swapping
75
Table 7: Lane Sequence
75
Programmable Transmit and Receive Equalization
76
Transmit Drive Level and Equalization
76
Receive Equalization
77
Figure 14: Drive Strength and Equalization Waveform
77
Port Loopback Testing
78
Figure 15: Tsi574 Loopbacks
78
Digital Equipment Loopback
79
Logical Line Loopback
79
Bit Error Rate Testing (BERT)
79
BERT Pattern Generator
79
Table 8: Patterns Supported by Generator
79
BERT Pattern Matcher and Error Counter
81
Fixed Pattern-Based BERT
81
Table 9: Patterns Supported by Matcher
81
Using PRBS Scripts for the Transmitters and Receivers
82
Internal Switching Fabric
83
Overview
83
Functional Behavior
84
Figure 16: ISF Block Diagram
84
Transfer Modes
85
Arbitration for Egress Port
86
Strict Priority Arbitration
86
Figure 17: Egress Arbitration: Weighted Round Robin and Strict Priority
86
Weighted Round Robin (WRR) Arbitration
87
Figure 18: Weighted Round Robin Arbiter Per Priority Group
87
Table 10: Sample Register Settings for WRR in a Given Priority Group (WRR_EN=1)
88
Packet Queuing
89
Output Queuing on the Egress Port
89
Figure 19: Ingress and Egress Packet Queues in Tsi574
89
Table 11: Examples of Use of Watermarks
91
Input Queue for the ISF Port
92
Input Arbitration
93
Input Queuing Model for the Multicast Work Queue
97
Input Queuing Model for the Broadcast Buffer
98
Output Queuing Model for Multicast
98
ISF Bandwidth
98
Multicast
101
Overview
101
Multicast Operation
101
Features
101
Multicast Operation with Multiple Tsi57X Switches
102
Figure 20: Multicast Operation - Option 1
102
Multicast Terminology
103
Figure 21: Multicast Operation - Option 2
103
Table 12: Multicast Terminology
103
Multicast Behavior Overview
104
Multicast Work Queue
105
Broadcast Buffers
105
Figure 22: Multicast Packet Flow in the Tsi574
106
Multicast Group Tables
108
Configuring Basic Associations
110
Figure 23: Relationship Representation
110
Configuring Multicast Masks
111
Figure 24: Completed Tables at the End of Configuration
112
Configuring Multicast Masks Using the IDT Specific Registers
114
Arbitration for Multicast Engine Ingress Port
115
Figure 25: IDT-Specific Multicast Mask Configuration
115
Error Management of Multicast Packets
116
Packet TEA
116
Multicast Packet Stomping
116
Figure 26: Arbitration Algorithm for Multicast Port
116
Multicast Maximum Latency Timer
117
Silent Discard of Packets
118
Port-Writes and Multicast
118
Port Reset
118
Event Notification
119
Overview
119
Event Summary
120
Table 13: Tsi574 Events
120
Error Rate Thresholds
124
Maintaining Packet Flow
125
Error Stopped State Recovery
126
Error Stopped States
126
Link Error Clearing and Recovery
127
Figure 27: Control Symbol Format
128
Event Capture
129
Table 14: Error Rate Error Events
130
Port-Write Notifications
131
Destination ID
132
Payload
132
Servicing Port-Writes
133
Table 15: Port Write Packet Data Payload - Error Reporting
133
Port-Writes and Hot Insertion/Hot Extraction Notification
134
Port-Writes and Multicast
134
Interrupt Notifications
134
Figure 28: Rapidio Block Interrupt and Port Write Hierarchy
135
Int_B Signal
136
Global Interrupt Status Register and Interrupt Handling
136
Table 16: Port X Error and Status Register Status
137
Interrupt Notification and Port-Writes
138
Reset Control Symbol and Interrupt Handling
138
I 2 C Interface
139
Overview
139
Protocol Overview
141
Block Diagram
142
Figure 29: I 2 C Block Diagram
143
Figure 30: I 2 C Reference Diagram
144
Tsi574 as I 2 C Master
145
Figure 31: Software-Initiated Master Transactions
146
Example EEPROM Read and Write
147
Master Clock Generation
147
Master Bus Arbitration
148
Master External Device Addressing
148
Master Peripheral Addressing
148
Master Data Transactions
149
Tsi574 as I 2 C Slave
149
Slave Clock Stretching
151
Figure 32: Transaction Protocols for Tsi574 as Slave
151
Slave Device Addressing
152
Slave Peripheral Addressing
152
External I C Register Map
153
Slave Write Data Transactions
154
Slave Read Data Transactions
155
Slave Internal Register Accesses
155
Slave Access Examples
156
Resetting the I 2 C Slave Interface
159
Mailboxes
159
Figure 33: I 2 C Mailbox Operation
160
Table 17: Externally Visible I
160
Incoming Mailbox
161
Outgoing Mailbox
161
Smbus Support
161
Unsupported Smbus Features
162
Smbus Protocol Support
162
Figure 34: Smbus Protocol Support
163
Smbus Alert Response Protocol Support
164
Boot Load Sequence
164
Figure 35: Smbus Alert Response Protocol
164
Figure 36: Boot Load Sequence
165
Idle Detect
166
EEPROM Reset Sequence
166
Wait for Bus Idle
166
EEPROM Device Detection
167
Loading Register Data from EEPROM
167
Chaining
168
EEPROM Data Format
168
Table 18: Format for Boot Loadable EEPROM
169
Table 19: Sample EEPROM Loading Two Registers
169
I2C Boot Time
170
Table 20: Sample EEPROM with Chaining
170
Accelerating Boot Load
171
Error Handling
172
Table 21: I 2 C Error Handling
172
Interrupt Handling
174
Figure 37: I 2 C Interrupt Generation
174
Events Versus Interrupts
175
Figure 38: I 2 C Event and Interrupt Logic
176
Timeouts
177
Table 22: I 2 C Interrupt to Events Mapping
177
Figure 39: I 2 C Timeout Periods
180
Bus Timing
181
Figure 40: I 2 C Bus Timing Diagrams
182
Start/Restart Condition Setup and Hold
183
Stop Condition Setup
183
I2C_SD Setup and Hold
183
I2C_SCLK Nominal and Minimum Periods
184
Idle Detect Period
184
Performance
185
Overview
185
Throughput
185
Latency
185
Performance Monitoring
186
Figure 41: Latency Illustration
186
Table 23: Performance Monitoring Parameters
187
Traffic Efficiency
188
Throughput
188
Bottleneck Detection
189
Congestion Detection
189
Resetting Performance Registers
189
Configuring the Tsi574 for Performance Measurements
190
Clock Speeds
190
Tsi574 ISF Arbitration Settings
190
Tsi574 Rapidio Transmission Scheduler Settings
191
Tsi574 Rapidio Buffer Watermark Selection Settings
191
Port-To-Port Performance Characteristics
191
Port-To-Port Packet Latency Performance
191
Packet Throughput Performance
192
Table 24: 4X/1X Latency Numbers under no Congestion
192
Multicast Performance
193
Congestion Detection and Management
194
Table 25: 4X/1X Multicast Latency Numbers under no Congestion
194
Figure 42: Congestion and Detection Flowchart
195
Congestion Registers
196
Figure 43: Congestion Example
198
JTAG Interface
199
Overview
199
JTAG Device Identification Number
200
JTAG Register Access Details
200
Format
200
Figure 44: Register Access from JTAG - Serial Data in
200
Figure 45: Register Access from JTAG - Serial Data out
200
Write Access to Registers from the JTAG Interface
201
Read Access to Registers from the JTAG Interface
201
Clocks, Resets and Power-Up Options
203
Clocks
203
Clocking Architecture
204
Figure 46: Tsi574 Clocking Architecture
204
Serdes Clocks
205
Reference Clocks
205
Table 26: Tsi574 Input Reference Clocks
205
Clock Domains
206
Clock Gating
206
Table 27: Tsi574 Clock Domains
206
Resets
207
Device Reset
207
Per-Port Reset
209
Generating a Rapidio Reset Request to a Peer Device
209
JTAG Reset
209
Power-Up Options
210
Power-Up Option Signals
210
Table 28: Power-Up Options Signals
211
Default Port Speed
212
Port Power-Up and Power-Down
212
Port Width Override
212
Signals
213
Overview
213
Table 29: Signal Types
213
Endian Ordering
214
Port Numbering
214
Signal Groupings
214
Table 30: Tsi574 Port Numbering
214
Table 31: Tsi574 Signal Descriptions
215
Pinlist and Ballmap
223
Serial Rapidio Registers
225
Overview
225
Table 32: Address Rules
225
Reserved Register Addresses and Fields
226
Table 33: Register Access Types
226
Port Numbering
227
Conventions
227
Table 34: Port Numbering
227
Register Map
228
Table 35: Register Map Overview
228
Table 36: Register Map
229
Rapidio Logical Layer and Transport Layer Registers
238
Rapidio Device Identity CAR
239
Rapidio Device Information CAR
240
Rapidio Assembly Identity CAR
241
Rapidio Assembly Information CAR
242
Rapidio Processing Element Features CAR
243
Rapidio Switch Port Information CAR
245
Rapidio Source Operation CAR
246
Rapidio Switch Multicast Support CAR
248
Rapidio Route LUT Size CAR
249
Rapidio Switch Multicast Information CAR
250
Rapidio Host Base Device ID Lock CSR
251
Rapidio Component Tag CSR
252
Rapidio Route Configuration Destid CSR
253
Rapidio Route Configuration Output Port CSR
254
Rapidio Route LUT Attributes (Default Port) CSR
255
Rapidio Multicast Mask Configuration Register
256
Rapidio Multicast Destid Configuration Register
258
Rapidio Multicast Destid Association Register
259
Rapidio Physical Layer Registers
261
Table 37: Physical Interface Register Offsets
261
Rapidio 1X or 4X Switch Port Maintenance Block Header
262
Rapidio Switch Port Link Timeout Control CSR
263
Rapidio Switch Port General Control CSR
264
Rapidio Serial Port X Link Maintenance Request CSR
265
Rapidio Serial Port X Link Maintenance Response CSR
267
Rapidio Serial Port X Local Ackid Status CSR
268
Rapidio Port X Error and Status CSR
270
Rapidio Serial Port X Control CSR
273
Rapidio Error Management Extension Registers
277
Table 38: Error Management Registers
277
Port Behavior When Error Rate Failed Threshold Is Reached
278
Table 39: STOP_FAIL_EN and DROP_EN Setting
278
Rapidio Error Reporting Block Header
279
Rapidio Logical and Transport Layer Error Detect CSR
280
Rapidio Logical and Transport Layer Error Enable CSR
281
Rapidio Logical and Transport Layer Address Capture CSR
282
Rapidio Logical and Transport Layer Device ID Capture CSR
283
Rapidio Logical and Transport Layer Control Capture CSR
284
Rapidio Port-Write Target Device ID CSR
285
Rapidio Port X Error Detect CSR
286
Rapidio Port X Error Rate Enable CSR
289
Rapidio Port X Error Capture Attributes CSR and Debug 0
291
Table 40: ERR_TYPE Values
291
Rapidio Port X Packet and Control Symbol Error Capture CSR 0 and Debug 1
293
Rapidio Port X Packet Error Capture CSR 1 and Debug 2
294
Rapidio Port X Packet Error Capture CSR 2 and Debug 3
294
Rapidio Port X Packet Error Capture CSR 3 and Debug 4
295
Rapidio Port X Error Rate CSR
296
Rapidio Port X Error Rate Threshold CSR
298
IDT-Specific Rapidio Registers
299
Table 41: IDT-Specific Broadcast Rapidio Registers
299
Table 42: IDT-Specific Per-Port Performance Registers
300
Rapidio Port X Discovery Timer
301
Rapidio Port X Mode CSR
302
Rapidio Port X Multicast-Event Control Symbol and Reset Control Symbol Interrupt CSR
304
Rapidio Port X Rapidio Watermarks
305
Rapidio Port X Route Config Destid CSR
306
Rapidio Port X Route Config Output Port CSR
307
Rapidio Port X Local Routing LUT Base CSR
308
Rapidio Multicast Write ID X Register
309
Rapidio Multicast Write Mask X Register
310
Rapidio Port X Control Independent Register
311
Rapidio Port X Send Multicast-Event Control Symbol Register
314
Rapidio Port X LUT Parity Error Info CSR
315
Rapidio Port X Control Symbol Transmit
317
Rapidio Port X Interrupt Status Register
318
Rapidio Port X Interrupt Generate Register
321
IDT-Specific Performance Registers
323
Table 43: IDT-Specific Per-Port Performance Registers
323
Rapidio Port X Performance Statistics Counter 0 and 1 Control Register
324
Rapidio Port X Performance Statistics Counter 2 and 3 Control Register
328
Rapidio Port X Performance Statistics Counter 4 and 5 Control Register
332
Rapidio Port X Performance Statistics Counter 0 Register
336
Rapidio Port X Performance Statistics Counter 1 Register
337
Rapidio Port X Performance Statistics Counter 2 Register
338
Rapidio Port X Performance Statistics Counter 3 Register
339
Rapidio Port X Performance Statistics Counter 4 Register
340
Rapidio Port X Performance Statistics Counter 5 Register
341
Rapidio Port X Transmitter Output Queue Depth Threshold Register
342
Rapidio Port X Transmitter Output Queue Congestion Status Register
344
Rapidio Port X Transmitter Output Queue Congestion Period Register
346
Rapidio Port X Receiver Input Queue Depth Threshold Register
347
Rapidio Port X Receiver Input Queue Congestion Status Register
349
Rapidio Port X Receiver Input Queue Congestion Period Register
351
Rapidio Port X Reordering Counter Register
352
Serial Port Electrical Layer Registers
353
Table 44: IDT-Specific Rapidio Registers
353
Table 45: Serial Port Electrical Layer Registers
353
BYPASS_INIT Functionality
354
SRIO MAC X Serdes Configuration Channel 0
355
SRIO MAC X Serdes Configuration Channel 1
358
SRIO MAC X Serdes Configuration Channel 2
360
SRIO MAC X Serdes Configuration Channel 3
362
SRIO MAC X Serdes Configuration Global
364
Table 46: TX_LVL Values
365
Table 47: AC JTAG Level Programmed by ACJT_LVL[4:0]
366
SRIO MAC X Serdes Configuration Globalb
368
SRIO MAC X Digital Loopback and Clock Selection Register
369
Internal Switching Fabric (ISF) Registers
372
Fabric Control Register
372
Fabric Interrupt Status Register
374
Rapidio Broadcast Buffer Maximum Latency Expired Error Register
375
Rapidio Broadcast Buffer Maximum Latency Expired Override
376
Utility Unit Registers
377
Global Interrupt Status Register
377
Global Interrupt Enable Register
379
Rapidio Port-Write Timeout Control Register
380
Rapidio Port Write Outstanding Request Register
381
MCES Pin Control Register
382
Multicast Registers
383
Rapidio Multicast Register Version CSR
383
Rapidio Multicast Maximum Latency Counter CSR
384
Rapidio Port X ISF Watermarks
385
Port X Prefer Unicast and Multicast Packet Prio 0 Register
386
Port X Prefer Unicast and Multicast Packet Prio 1 Register
387
Port X Prefer Unicast and Multicast Packet Prio 2 Register
388
Port X Prefer Unicast and Multicast Packet Prio 3 Register
389
Serdes Per Lane Register
390
Table 48: Serdes Register Map
390
Serdes Lane 0 Pattern Generator Control Register
391
Serdes Lane 1 Pattern Generator Control Register
392
Serdes Lane 2 Pattern Generator Control Register
393
Serdes Lane 3 Pattern Generator Control Register
394
Serdes Lane 0 Pattern Matcher Control Register
395
Serdes Lane 1 Pattern Matcher Control Register
396
Serdes Lane 2 Pattern Matcher Control Register
397
Serdes Lane 3 Pattern Matcher Control Register
398
Serdes Lane 0 Frequency and Phase Value Register
399
Serdes Lane 1 Frequency and Phase Value Register
400
Serdes Lane 2 Frequency and Phase Value Register
401
Serdes Lane 3 Frequency and Phase Value Register
402
I2C Registers
403
Register Map
403
Table 49: I 2 C Register Map
403
Register Descriptions
406
I 2 C Device ID Register
406
I 2 C Reset Register
407
I 2 C Master Configuration Register
408
I 2 C Master Control Register
410
Table 50: Master Operation Sequence
412
I 2 C Master Receive Data Register
413
I 2 C Master Transmit Data Register
414
I 2 C Access Status Register
415
I 2 C Interrupt Status Register
418
I 2 C Interrupt Enable Register
421
I 2 C Interrupt Set Register
423
I 2 C Slave Configuration Register
425
I 2 C Boot Control Register
428
Externally Visible I C Internal Write Address Register
432
Externally Visible I C Internal Write Data Register
433
Externally Visible I C Internal Read Address Register
434
Externally Visible I
434
Internal Read Data Register
435
Externally Visible I
435
Slave Access Status Register
436
Externally Visible I C Internal Access Control Register
438
Externally Visible I
438
Status Register
440
Externally Visible I
440
Enable Register
443
Externally Visible I C Outgoing Mailbox Register
446
Externally Visible I C Incoming Mailbox Register
447
I 2 C Event and Event Snapshot Registers
448
I 2 C New Event Register
452
I 2 C Enable Event Register
455
I 2 C Time Period Divider Register
458
I 2 C Start Condition Setup/Hold Timing Register
459
I 2 C Stop/Idle Timing Register
460
I2C_SD Setup and Hold Timing Register
461
I2C_SCLK High and Low Timing Register
462
I2C_SCLK Minimum High and Low Timing Register
463
I2C_SCLK Low and Arbitration Timeout Register
464
I 2 C Byte/Transaction Timeout Register
465
I 2 C Boot and Diagnostic Timer
466
I 2 C Boot Load Diagnostic Progress Register
467
I 2 C Boot Load Diagnostic Configuration Register
468
Serial Rapidio Protocol Overview
469
Protocol
469
Packets
469
Control Symbols
470
Physical Layer
470
PCS Layer
470
PMA Layer
470
Physical Protocol
470
Table 51: Special Characters and Encoding
471
Table 52: Control Symbol Construction
472
Clocking
475
Line Rate Support
475
Table 53: Tsi574 Supported Line Rates
475
Register Requirements Using 125 Mhz S_CLK for a 3.125 Gbps Link Rate
476
P_CLK Programming
479
Rapidio Specifications Directly Affected by Changes in the P_CLK Frequency
479
Table 54: Timer Values with P_CLK and TVAL Variations
480
Table 55: Timer Values with DISCOVERY_TIMER and P_CLK Variations
481
IDT Specific Timers
482
Table 56: Timer Values with P_CLK and DLT_THRESH Variations
482
I 2 C Interface and Timers
483
Other Performance Factors
489
PRBS Scripts
491
Tsi574_Start_Prbs_All.txt Script
491
Tsi574_Framer_Disable.txt Script
493
Tsi574_Sync_Prbs_All.txt Script
494
Tsi574_Read_Prbs_All.txt Script
497
EEPROM Scripts
501
Script
501
Index
509

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