Serdes Control And Status Registers - Renesas IDT 89HPES48H12G2 User Manual

IDT Switch Configuration and Status Registers

SerDes Control and Status Registers

Refer to Chapter 8, SerDes, for a details on programming SerDes controls. Note that in order to program the SerDes controls for a given port,
it is necessary to identify which SerDes block is associated with the port. Refer to section SerDes Numbering and Port Association on page 8-1
for details.
S[13:12, 9:0]CTL - SerDes x Control
Bit
Field Name
4:0 LANESEL
5 POWERDN
31:6 Reserved
PES48H12G2 User Manual
Field Default
Type
Value
RW 0x10
SWSticky
RW 0x0
SWSticky
RO 0x0
Description
Lane Select. This field selects the lane on which the SerDes lane
control registers (S[x]TXLCTL0, S[x]TXLCTL1, S[x]RXLCTL, and
S[x]RXEQLCTL) operate when written.
0x0 - Operate on lane 0 only
0x1 - Operate on lane 1 only
0x2 - Operate on lane 2 only
0x3 - Operate on lane 3 only
0x10 - Operate on all lanes simultaneously
Others - Reserved
For example, when LANESEL=0x0, configuration writes to the
above listed registers affect lane 0 of the SerDes only. When
LANESEL=0x10, the settings in the SerDes lane control registers
are applied to all lanes simultaneously.
Read operations are not affected by this field (i.e., reading from a
SerDes lane control register returns the last value written to that
register, regardless of the setting of this field).
Operating on a reserved lane results in undefined consequences.
SerDes Power-Down. When this bit is set, the SerDes is placed in
a deep low-power state (i.e., the SerDes lanes are placed in P2
and the CMU is powered-down). In addition, the PHY LTSSM in
the corresponding port(s) is immediately transitioned to the Detect
state.
When this bit is cleared, the SerDes is powered-on, initialized, and
the PHY LTSSM initiates link training.
This bit has no effect when the SerDes is already powered-down
(e.g., the SerDes quad associated with a disabled port).
When a SerDes is powered-down, the serial Tx/Rx pins and refer-
ence resistor pins may be left unconnected.
Refer to section SerDes Power Management on page 8-15 for fur-
ther details on SerDes power management.
Reserved field.
17 - 8 April 5, 2013