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IDT Reset and Initialization
Notes
PES48H12G2 User Manual
• If the link associated with a downstream port is in the Disabled LTSSM state, then a hot reset
will not be propagated out on that port. The port will instead transition to the Detect LTSSM state.
Although not a hot reset, this has the same functional effect on downstream components.
2. All registers fields in all registers associated with downstream ports, except those designated Sticky
and SWSticky, are reset to their initial value. The value of fields designated Sticky or SWSticky is
unaffected by an Upstream Secondary Bus Reset.
3. All TLPs received from downstream ports and queued in the PES48H12G2 are discarded.
4. Logic in the stack and switch core associated with the downstream ports are gracefully reset.
5.
Wait for software to clear the Secondary Bus Reset (SRESET) bit in the upstream port's Bridge
Control Register (BCTL).
6. Normal downstream port operation begins.
The operation of the upstream port is unaffected by a secondary bus reset. The link remains up and
Type 0 configuration read and write transactions that target the upstream port complete normally.
During an Upstream Secondary Bus Reset, all TLPs destined to the secondary side of the upstream
port's PCI-to-PCI bridge are treated as unsupported requests.
The operation of the slave SMBus interface is unaffected by an Upstream Secondary Bus Reset. Using
the slave SMBus to access a register that is reset by an Upstream Secondary Bus Reset causes the
register's default value to be returned on a read and written data to be ignored on writes.
Partition Downstream Secondary Bus Reset
A partition downstream secondary bus reset may be initiated by the following condition:
– A one is written to the Secondary Bus Reset (SRESET) bit in a downstream port's Bridge Control
Register (BCTL).
When a Downstream Secondary Bus Reset occurs, the following sequence of actions take place on
logic associated with the affected partition.
– If the corresponding downstream port's link is up, TS1 ordered sets with the hot reset bit set are
transmitted
– All TLPs received from corresponding downstream port and queued are discarded.
– Wait for software to clear the Secondary Bus Reset (SRESET) bit in the downstream port's Bridge
Control Register (BCTL).
– Normal downstream port operation begins.
The operation of the upstream port is unaffected by a partition downstream secondary bus reset. The
operation of other downstream ports in this and other partitions is unaffected by a partition downstream
secondary bus reset. During a partition downstream secondary bus reset, Type 0 configuration read and
write transactions that target the downstream port complete normally. During a partition downstream
secondary bus reset, all TLPs destined to the secondary side of the downstream port's PCI-to-PCI bridge
are treated as unsupported requests.
Port Mode Change Reset
A port mode change reset occurs when a port operating mode change is initiated and the OMA field in
the corresponding SWPORTxCTL register specifies a reset. Port mode change reset behavior is described
in section Reset Mode Change Behavior on page 6-14.
5 - 10
April 5, 2013
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