General Purpose I/O Registers - Renesas IDT 89HPES48H12G2 User Manual

IDT Switch Configuration and Status Registers
S[13:12, 9:0]RXEQLCTL - SerDes x Receiver Equalization Lane Control
Bit
Field Name
2:0
5:3 RXEQB
31:6 Reserved

General Purpose I/O Registers

GPIOFUNC0 - General Purpose I/O Function 0 (0x0A90)
Bit
Field Name
8:0 GPIOFUNC
31:9 Reserved
PES48H12G2 User Manual
Field Default
Type
Value
RXEQZ RW 0x1
SWSticky
RW 0x7
SWSticky
RO 0x0
Field Default
Type
Value
RW 0x0
SWSticky
RW
Description
Receiver Equalization Zero. Amplifies the high-frequency gain of
the equalizer. A value of 0x0 results in the smallest amount of high
frequency gain. A value of 0x7 results in the highest amount of
high frequency gain. Together with the other fields in this register,
the default value corresponds to a long, lossy channel.
Setting both RXEQZ and RXEQB to zero results in turning off
receiver equalization completely.
Refer to section Receiver Equalization Controls on page 8-14 for
further information of Receiver Equalization.
This field controls the receiver equalization for the lane(s) selected
by the Lane Select (LANESEL) field in the SerDes Control
(S[x]CTL) register. This value is SWSticky for all lanes (i.e., even
those not selected by the LANESEL field in the S[x]CTL register).
Receive Equalization Boost. Reduces the low-frequency gain of
the equalizer. A value of 0x0 results in the largest low frequency
gain and smallest amount of boost. A value of 0x7 results in the
smallest low frequency gain and largest amount of boost. Together
with the other fields in this register, the default value corresponds
to a long, lossy channel.
Setting both RXEQZ and RXEQB to zero results in turning off
receiver equalization completely.
Refer to section Receiver Equalization Controls on page 8-14 for
further information of Receiver Equalization.
This field controls the receiver equalization for the lane(s) selected
by the Lane Select (LANESEL) field in the SerDes Control
(S[x]CTL0) register. This value is SWSticky for all lanes (i.e., even
those not selected by the LANESEL field in the S[x]CTL0 register).
Reserved field.
Description
GPIO Function. Each bit in this field controls the corresponding
GPIO pin. When set, the corresponding GPIO pin operates as the
selected alternate function. When a bit is cleared, the correspond-
ing GPIO pin operates as a general purpose I/O pin.
Bit x in this field corresponds to GPIO pin x.
Reserved field.
17 - 15 April 5, 2013