Page 1 ® ® 89HPES48H12AG2 ® PCI Express Switch User Manual April 2013 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2013 Integrated Device Technology, Inc.
Page 2 GENERAL DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use.
Page 3: About This Manual
About This Manual ® Introduction Notes This user manual includes hardware and software information on the 89HPES48H12AG2, a member of IDT’s PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O interconnect standard. Finding Additional Information Information not included in this manual such as mechanicals, package pin-outs, and electrical character- istics can be found in the data sheet for this device, which is available from the IDT website (www.idt.com) as well as through your local IDT sales representative.
Page 4: Signal Nomenclature
Notes Chapter 17, “Switch Control and Status Registers,” lists the switch control and status registers in the PES48H12AG2 and provides a description of each bit in those registers. Chapter 18, “JTAG Boundary Scan,” discusses an enhanced JTAG interface, including a system logic TAP controller, signal definitions, a test data register, an instruction register, and usage considerations.
Page 5: Register Terminology
Notes Term Words Bytes Bits Byte Word Doubleword (Dword) Quadword (Qword) Table 1 Data Unit Terminology In quadwords, bit 63 is always the most significant bit and bit 0 is the least significant bit. In double- words, bit 31 is always the most significant bit and bit 0 is the least significant bit. In words, bit 15 is always the most significant bit and bit 0 is the least significant bit.
Page 6 Notes Type Abbreviation Description Hardware Initialized HWINIT Register bits are initialized by firmware or hardware mechanisms such as pin strapping or serial EEPROM. (System firmware hard- ware initialization is only allowed for system integrated devices.) Bits are read-only after initialization and can only be reset (for write-once by firmware) with reset.
Page 7: Use Of Hypertext
Use of Hypertext Notes In Chapter 15, Tables 15.4, 15.5 and 15.6 contain register names and page numbers highlighted in blue under the Register Definition column. In pdf files, users can jump from this source table directly to the regis- ters by clicking on the register name in the source table.
Page 8 Notes June 16, 2009: In Chapter 5, revised Table 5.1 and revised text in sections Partition Hot Reset and Port Mode Change Reset. In Chapter 6, revised text in the following sections: Partition State, Partition State Change via Other Methods, Port Operating Mode Change via EEPROM Loading, Port Operating Mode Change via Other Methods, and Dynamic Reconfiguration.
Page 9 Notes July 8, 2011: In Chapter 16, removed table footnotes from PCISTS and SECSTS registers, added Reserved bits 31:24 to AERUEM and AERUESV registers, and added last sentence to each description in the PCIESCTLIV register. In Chapter 17, added FEN and fields to SWPART[x]CTL register and FCAPSEL SWPORT[x]CTL registers, added PFAILOVER and SFAILOVER fields to SWPART[X]STS register and...
Page 10 Notes PES48H12AG2 User Manual April 5, 2013...
Page 11: Table Of Contents
Table of Contents ® About This Manual Notes Introduction ............................ 1 Content Summary .......................... 1 Signal Nomenclature ........................2 Numeric Representations ......................2 Data Units ............................2 Register Terminology ........................3 Use of Hypertext ..........................5 Reference Documents ........................5 Revision History ..........................
Page 12 IDT Table of Contents Notes End-to-End Data Path Parity Protection ................3-14 Clocking Introduction ............................. 4-1 Port Clocking Modes........................4-2 Spread Spectrum Clocking (SSC) Support ................4-2 Global Clocked Mode ......................4-4 Local Port Clocked Mode ....................... 4-5 Modification of a Port’s Clock Mode ..................4-6 Reset and Initialization Introduction .............................
Page 13 IDT Table of Contents Notes Upstream Port ........................7-10 Downstream Port........................7-10 Link States ............................ 7-11 Active State Power Management ....................7-11 L0s ASPM..........................7-12 L1 ASPM ..........................7-12 L1 ASPM Entry Rejection Timer ....................7-13 Link Status ............................ 7-14 De-emphasis Negotiation ......................
Page 14 IDT Table of Contents Notes Power Good Controlled Reset Output .................. 10-6 Hot-Plug Events..........................10-6 Legacy System Hot-Plug Support....................10-7 Hot-Swap ............................10-8 Power Management Introduction ........................... 11-1 PME Messages..........................11-3 PCI Express Power Management Fence Protocol ............... 11-3 Upstream Switch Port or Downstream Switch Port Mode ............ 11-3 Power Budgeting Capability......................
Page 15 IDT Table of Contents PCI to PCI Bridge and Proprietary Port Specific Registers Notes Type 1 Configuration Header Registers ..................16-1 PCI Express Capability Structure ....................16-11 Power Management Capability Structure ................... 16-27 Message Signaled Interrupt Capability Structure ............... 16-29 Subsystem ID and Subsystem Vendor ID ..................
Page 16 IDT Table of Contents Notes PES48H12AG2 User Manual April 5, 2013...
Page 17 List of Tables ® Table 1.1 Initial Configuration Register Settings for PES48H12AG2 ..........1-4 Notes Table 1.2 PES48H12AG2 Device IDs ....................1-6 Table 1.3 PES48H12AG2 Revision ID ....................1-6 Table 1.4 PCI Express Interface Pins....................1-7 Table 1.5 Reference Clock Pins ......................1-8 Table 1.6 SMBus Interface Pins ......................
Page 18 IDT List of Tables Notes Table 10.1 Port Hot Plug Signals ......................10-3 Table 10.2 Negated Value of Unused Hot-Plug Output Signals............10-4 Table 11.1 PES48H12AG2 Power Management State Transition Diagram........11-2 Table 12.1 GPIO Pin Configuration ..................... 12-1 Table 12.2 General Purpose I/O Pin Alternate Function ..............
Page 19 List of Figures ® Figure 1.1 PES48H12AG2 Block Diagram ..................1-3 Notes Figure 1.2 PES48H12AG2 Logic Diagram ..................1-5 Figure 2.1 PES48H12AG2 Block Diagram ..................2-1 Figure 2.2 Transparent PCIe Switch ....................2-2 Figure 2.3 Partitionable PCI Express Switch ..................2-2 Figure 3.1 Crossbar Connection to Port Ingress and Egress Buffers ..........3-3 Figure 3.2 Architectural Model of Arbitration ..................3-6 Figure 3.3...
Page 20 IDT List of Figures Notes Figure 10.6 PES48H12AG2 Hot-Plug Event Signalling ..............10-8 Figure 11.1 PES48H12AG2 Power Management State Transition Diagram ........11-2 Figure 13.1 Split SMBus Interface Configuration ................13-1 Figure 13.2 Single Double Word Initialization Sequence Format ............13-3 Figure 13.3 Sequential Double Word Initialization Sequence Format ..........13-4 Figure 13.4 Configuration Done Sequence Format ................13-4 Figure 13.5...
Page 21 Register List ® ACSCAP - ACS Capability Register (0x324)..................16-49 Notes ACSCTL - ACS Control Register (0x326)..................... 16-51 ACSECAPH - ACS Extended Capability Header (0x320) ..............16-49 ACSECV - ACS Egress Control Vector (0x328)................... 16-52 AERCAP - AER Capabilities (0x100) ....................16-32 AERCEM - AER Correctable Error Mask (0x114) ................
Page 22 IDT Register List Notes IERRORSTS - Internal Error Reporting Status (0x484) ................16-59 IERRORTST - Internal Error Reporting Test (0x490)................16-65 INTRLINE - Interrupt Line Register (0x03C) ...................16-9 INTRPIN - Interrupt PIN Register (0x03D) ....................16-9 IOBASE - I/O Base Register (0x01C)......................16-5 IOBASEU - I/O Base Upper Register (0x030)..................16-8 IOEXPADDR0 - SMBus I/O Expander Address 0 (0x0AD8)..............17-26 IOEXPADDR1 - SMBus I/O Expander Address 1 (0x0ADC) ..............17-27 IOEXPADDR2 - SMBus I/O Expander Address 2 (0x0AE0) ..............17-27...
Page 23 IDT Register List Notes PCIESSTS2 - PCI Express Slot Status 2 (0x07A) ................16-27 PCIEVCECAP - PCI Express VC Enhanced Capability Header (0x200) ..........16-42 PCISTS - PCI Status Register (0x006) ....................16-2 PCLKMODE - Port Clocking Mode (0x0008) ..................17-3 PHYLCFG0 - Phy Link Configuration 0 (0x530)..................16-68 PHYLSTATE0 - Phy Link State 0 (0x540).....................16-69 PHYPRBS - Phy PRBS Seed (0x55C)....................16-69 PLTIMER - Primary Latency Timer (0x00D)....................16-4...
Page 24 IDT Register List Notes VID - Vendor Identification Register (0x000)...................16-1 PES48H12AG2 User Manual April 5, 2013...
Page 25: Pes48H12Ag2 Device Overview
Chapter 1 PES48H12AG2 Device Overview ® Introduction Notes The 89HPES48H12AG2 is a member of the IDT PRECISE™ family of PCI Express® switching solu- tions. The PES48H12AG2 is a 48-lane, 12-port system interconnect switch optimized for PCI Express Gen2 packet switching in high-performance applications, supporting multiple simultaneous peer-to-peer traffic flows.
Page 26 IDT PES48H12AG2 Device Overview Notes • De-emphasis • Receive equalization • Drive strength Switch Partitioning  – IDT proprietary feature that creates logically independent switches in the device – Supports up to 12 fully independent switch partitions – Configurable downstream port device numbering –...
Page 27 IDT PES48H12AG2 Device Overview – SerDes power savings • Supports low swing / half-swing SerDes operation • SerDes optionally turned-off in D3hot • SerDes associated with unused ports are turned-off • SerDes associated with unused lanes are placed in a low power state 54 General Purpose I/O ...
Page 28 IDT PES48H12AG2 Device Overview PCIELCAP Port MAXLNKWDTH Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 Port 11 Table 1.1 Initial Configuration Register Settings for PES48H12AG2 PES48H12AG2 User Manual 1 - 4 April 5, 2013...
Page 29: Logic Diagram
IDT PES48H12AG2 Device Overview Logic Diagram Global GCLKN[1:0] Reference Clocks GCLKP[1:0] GCLKFSEL PCI Express Switch P00CLKN PE00TP[3:0] PCI Express SerDes Output P00CLKP PE00TN3:[0] Switch Port 0 SerDes Input PE00RP[3:0] Port 0 PE00RN[3:0] PCI Express Switch PE01TP[3:0] SerDes Output PE01TN[3:0] P01CLKN PCI Express Port 1 Switch...
Page 30: System Identification
IDT PES48H12AG2 Device Overview System Identification Notes Vendor ID All vendor IDs in the device are hardwired to 0x111D which corresponds to Integrated Device Tech- nology, Inc. Device ID The PES48H12AG2 device ID is shown in Table 1.2. PCIe Device Device ID 0x14 0x807E...
Page 31: Pin Description
IDT PES48H12AG2 Device Overview Pin Description Notes The following tables list the functions of the pins provided on the PES48H12AG2. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N”...
Page 32: Table 1.5 Reference Clock Pins
IDT PES48H12AG2 Device Overview Notes Signal Type Name/Description PE07TP[3:0] PCI Express Port 7 Serial Data Transmit. Differential PCI Express trans- PE07TN[3:0] mit pairs for port 7. When port 6 is merged with port 7, these signals become port 6 transmit pairs for lanes 4 through 7. PE08RP[3:0] PCI Express Port 8 Serial Data Receive.
Page 33: Table 1.7 General Purpose I/O Pins
IDT PES48H12AG2 Device Overview Notes Signal Type Name/Description SSMBADDR[5,3:1] Slave SMBus Address. These pins determine the SMBus address to which the slave SMBus interface responds. SSMBCLK Slave SMBus Clock. This bidirectional signal is used to synchronize trans- fers on the slave SMBus. SSMBDAT Slave SMBus Data.
Page 34 IDT PES48H12AG2 Device Overview Notes Signal Type Name/Description GPIO[8] General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN Alternate function pin type: Input Alternate function: IO expander interrupt. GPIO[9] General Purpose I/O. This pin can be configured as a general purpose I/O pin.
Page 35 IDT PES48H12AG2 Device Overview Notes Signal Type Name/Description GPIO[19] General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: HP1PDN Alternate function pin type: Input Alternate function: Hot Plug Signal Group 1 Presence Detect Input. GPIO[20] General Purpose I/O.
Page 36 IDT PES48H12AG2 Device Overview Notes Signal Type Name/Description GPIO[27] General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: HP2APN 1st Alternate function pin type: Input 1st Alternate function: Hot Plug Signal Group 2 Attention Push Button Input.
Page 37 IDT PES48H12AG2 Device Overview Notes Signal Type Name/Description GPIO[34] General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: HP2PEP 1st Alternate function pin type: Output 1st Alternate function: Hot Plug Signal Group 2 Power Enable Output. 2nd Alternate function pin name: P7LINKUPN 2nd Alternate function pin type: Output 2nd Alternate function: Port 7 Link Up Status Output.
Page 38 IDT PES48H12AG2 Device Overview Notes Signal Type Name/Description GPIO[41] General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: HP3AIN 1st Alternate function pin type: Output 1st Alternate function: Hot Plug Signal Group 3 Attention Indicator Output. 2nd Alternate function pin name: P10ACTIVEN 2nd Alternate function pin type: Output 2nd Alternate function: Port 10 Link Active Status Output.
Page 39: Table 1.8 System Pins
IDT PES48H12AG2 Device Overview Notes Signal Type Name/Description GPIO[50] General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: HP4AIN Alternate function pin type: Output Alternate function: Hot Plug Signal Group 4 Attention Indicator Output. GPIO[51] General Purpose I/O.
Page 40 IDT PES48H12AG2 Device Overview Notes Signal Type Name/Description P45MERGEN Port 4 and 5 Merge. P45MERGEN is an active low signal. It is pulled low internally. When this pin is low, port 4 is merged with port 5 to form a single x8 port. The Serdes lanes associated with port 5 become lanes 4 through 7 of port 4.
Page 41: Table 1.9 Test Pins
IDT PES48H12AG2 Device Overview Notes Signal Type Name/Description JTAG_TCK JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle. JTAG_TDI JTAG Data Input.
Page 42 IDT PES48H12AG2 Device Overview Notes Signal Type Name/Description REFRES08 Port 8 External Reference Resistor. Provides a reference for the Port 8 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis- tor should be connected from this pin to ground. REFRES09 Port 9 External Reference Resistor.
Page 43: Pin Characteristics
IDT PES48H12AG2 Device Overview Pin Characteristics Notes Note: Some input pads of the switch do not contain internal pull-ups or pull-downs. Unused SMBus and System inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation.
Page 44 IDT PES48H12AG2 Device Overview Notes Internal Function Pin Name Type Buffer Notes Type Resistor PCI Express PE08TP[3:0] PCIe Serial Link Interface (Cont.) differential PE09RN[3:0] PE09RP[3:0] PE09TN[3:0] PE09TP[3:0] PE10RN[3:0] PE10RP[3:0] PE10TN[3:0] PE10TP[3:0] PE11RN[3:0] PE11RP[3:0] PE11TN[3:0] PE11TP[3:0] GCLKN[1:0] HCSL Diff. Clock Refer to Table 10 Input in the GCLKP[1:0]...
Page 45 IDT PES48H12AG2 Device Overview Notes Internal Function Pin Name Type Buffer Notes Type Resistor EJTAG / JTAG JTAG_TCK LVTTL pull-up JTAG_TDI pull-up JTAG_TDO JTAG_TMS pull-up JTAG_TRST_N pull-up SerDes Refer- REFRES00 Analog ence Resistors REFRES01 REFRES02 REFRES03 REFRES04 REFRES05 REFRES06 REFRES07 REFRES08 REFRES09 REFRES10...
Page 46 IDT PES48H12AG2 Device Overview Notes PES48H12AG2 User Manual 1 - 22 April 5, 2013...
Page 47: Architectural Overview
Chapter 2 Architectural Overview ® Introduction Notes This section provides a high level architectural overview of the PES48H12AG2. An architectural block diagram of the PES48H12AG2 is shown in Figure 2.1. PCI Express Port s PCI Express Port s SerDes SerDes SerDes SerDes SerDes...
Page 48: Switch Partitioning
IDT Architectural Overview Switch Partitioning Notes The logical view of a PCIe switch is shown in Figure 2.2. A PCI switch contains one upstream port and one or more downstream ports. Each port is associated with a PCI-to-PCI bridge. All PCI-to-PCI bridges associated with a PCIe switch are interconnected by a virtual PCI bus.
Page 49: Dynamic Reconfiguration
IDT Architectural Overview Notes Each partition operates logically as a completely independent PCIe switch that implements the behavior and capabilities outlined in the PCI Express Base specification required of a switch. The PES48H12AG2 supports boot-time (i.e., Fundamental Reset) and runtime configuration of ports into partitions.
Page 50 IDT Architectural Overview Notes PES48H12AG2 User Manual 2 - 4 April 5, 2013...
Page 51: Switch Core
Chapter 3 Switch Core ® Introduction Notes This chapter provides an overview of the PES48H12AG2’s Switch Core. As shown in Figure 2.1 in the Architectural Overview chapter, the Switch Core interconnects switch ports. The Switch Core’s main func- tion is to transfer TLPs among these ports efficiently and reliably. In order to do so, the Switch Core provides buffering, ordering, arbitration, and error detection services.
Page 52: Egress Buffer
IDT Switch Core Notes Total Size and Advertised Advertised Port Limitations Data Header Mode Queue (per-port) Credits Credits Posted 12352 Bytes and up to 127 Merged TLPs Non Posted 2048 Bytes and up to 127 TLPs Completion 12352 Bytes and up to 127 TLPs Table 3.1 IFB Buffer Sizes (Part 2 of 2) Egress Buffer...
Page 53: Crossbar Interconnect
IDT Switch Core Notes Port Replay Buffer Storage Mode Limit 32 TLPs Bifurcated 64 TLPs Merged Table 3.3 Replay Buffer Storage Limit Crossbar Interconnect The crossbar is a 12x12 matrix of pathways, capable of concurrently transferring data between a maximum of 12 port pairs. The crossbar interconnects the port ingress buffers to the egress buffers. It provides two data-interfaces per port, one for the port’s ingress buffers and one for the port’s egress buffers.
Page 54: Packet Ordering
IDT Switch Core Notes (merged or bifurcated) and the width and speed of the port’s link. Packets received from the port are stored in the appropriate IFB queue. After being queued in an IFB and undergoing ordering and arbitration, all data transferred through the crossbar interconnect is transferred in a continuous TLP manner (i.e., the data path is never multiplexed).
Page 55: Arbitration
IDT Switch Core Notes Posted Non-Posted Request Completion Request IO or IO or Memory Configur Row Pass Column? Configur Read Write or Read ation ation Comple- Message Request Write Write tion Request Comple- Request tion Posted Memory Request Write or Message Request Non Posted...
Page 56: Port Arbitration
IDT Switch Core Notes Switch Core Port 0 IFB VC 0 Port 0 Egress Arbitration VC 0 Arbitration Port VC 0 Port 1 IFB (not Arbitration applicable) VC 0 Port 11 Port 7 Port 15 Egress Arbitration VC 0 Arbitration Port VC 0 (not...
Page 57: Table 3.5 Conditions For Cut-Through Transfers
IDT Switch Core Notes and egress link bandwidth is determined by the negotiated speed and width of the links. Table 3.5 shows the conditions under which cut-through and adaptive-cut-through occur. When the conditions are met, cut- through is performed across the IFB, crossbar , and EFB.
Page 58: Request Metering
IDT Switch Core Notes Ingress Ingress Egress Egress Conditions for Cut- Link Link Link Link Through Speed Width Speed Width 5.0 Gbps x8, x4, x2, x1 Always x8, x4, x2, x1 Always x8, x4, x2, x1 Always At least 50% of packet is in IFB x4, x2, x1 Always At least 50% of packet is in IFB...
Page 59 IDT Switch Core Notes If read requests are injected sporadically or at a low rate, then buffering within the switch may be used to accommodate short lived contention and allow completions to endpoints to proceed without interfering. If read requests are injected at a high rate, then no amount of buffering in the switch will prevent completions from interfering.
Page 60: Operation
IDT Switch Core Notes The request metering implementation in the PES48H12AG2 makes a number of simplifying assump- tions that may or may not be true in all systems. Therefore, it should be expected that some amount of parameter tuning may be required to achieve optimum performance. Note that tuning of the request metering mechanism should take into account the completion timeout value of the associated requesters (i.e., request metering should be tuned such that a requester’s comple- tion timeout value is not violated).
Page 61: Table 3.6 Request Metering Decrement Value
IDT Switch Core Notes The Decrement Value Adjustment (DVADJ) field represents a sign-magnitude fixed point 0:4:11 number (i.e., a positive fixed-point number with 4 integer bits and 11 fractional bits). – DVADJ field provides fine grain programmable adjustment of the value by which the counter is decremented.
Page 62: Completion Size Estimation
IDT Switch Core Notes tmp = RequestMeteringCounter RequestMeteringCounter (DecrementValue[LinkSpeed,LinkWidth] RMCTL.DVADJ) if (tmp < RequestMeteringCounter) { RequestMeteringCounter = 0 Figure 3.7 Request Metering Counter Decrement Operation Completion Size Estimation This section describes the value that is loaded into the request metering counter when a request is transferred into the switch core.
Page 63: Internal Errors
IDT Switch Core Notes If the number of data DWords is zero, then the completion size is estimated to be three DWords (i.e., a 0:13:3 representation value of 0x0018). – Otherwise, if the number of required data DWords is less than the Constant Limit (CNSTLIMIT) field in the RMCTL register, then the completion size is estimated as the number of required data DWords plus one.
Page 64: Switch Time-Outs
IDT Switch Core Notes To facilitate testing of software error handlers, any bit in the IERRORSTS register may be set by writing a one to the corresponding bit position in the Internal Error Test (IERRORTST) register. Once a bit is set in the ERRORSTS register, it is processed as though the actual error occurred (e.g., reported by AER).
Page 65 IDT Switch Core Notes As the TLP flows through the switch, its alignment or contents may be modified. In all such cases, parity is updated and not recomputed. Hence, any error that occurs is propagated and not masked by a parity regeneration.
Page 66 IDT Switch Core Notes PES48H12AG2 User Manual 3 - 16 April 5, 2013...
Page 67: Clocking
Chapter 4 Clocking ® Introduction Notes Figure 4.1 provides a logical representation of the PES48H12AG2 clocking architecture. The PES48H12AG2 has a single differential global reference clock input (GCLK) as well as a differential refer- ence clock input (PxCLK) per port. Port 0 Port 1 Port 2...
Page 68: Port Clocking Modes
IDT Clocking A port reference clock input is associated with each x4 port. When two x4 ports are merged to create a x8 port, the port reference clock input used by the merged port is that of the associated with the even port. The port reference clock input associated with the merged odd port is unused and should be connected to Vss on the system board..
Page 69: Table 4.2 Gclk And Pxclk Frequencies When Pxclk Has Ssc
IDT Clocking Nominal PxCLK Effective Allowed PxCLK PxCLK GCLK Frequency Modulation Frequency Frequency 100 MHz + 300ppm +0 / - 5000ppm 100 Mhz +300 / - 100 Mhz + / - 4700ppm 300ppm 100 MHz - 300ppm +0 / - 5000ppm 100 Mhz -300 / - 100 Mhz + / - 5300ppm...
Page 70: Global Clocked Mode
IDT Clocking PES48H12AG2 Switch Link Valid Port Partner Notes Port Global Config. Clocking Refclk Clock Clock Mode Local Port PxCLK with GCLK Same PxCLK as the Local port clocked with common Refclk architecture Clocked switch and SSC. Local Port PxCLK with GCLK with Same PxCLK or different Clocked...
Page 71: Local Port Clocked Mode
IDT Clocking Notes Switch GCLK Clock Generator Port Clock Link Partner Generator Figure 4.3 Clocking Connection for a Port in Global Clocked Mode, Non-Common Clocked Configuration Local Port Clocked Mode A port in local port clocked mode uses the corresponding port clock (PxCLK) input for receiving and transmitting serial data.
Page 72: Modification Of A Port's Clock Mode
IDT Clocking Notes Switch GCLK Clock Generator Port PxCLK Clock Generator Clock Link Partner Generator Figure 4.5 Clocking Connection for a Port in Local Port Clocked Mode, in a Non-Common Clocked Configuration Modification of a Port’s Clock Mode The clocking mode associated with a port may be modified at any time, with the only requirement being that the reference clock that will be used by the port after the port’s clocking mode is modified must be stable prior to the modification.
Page 73: Reset And Initialization
Chapter 5 Reset and Initialization ® Introduction Notes This chapter describes the PES48H12AG2 resets and initialization. There are two classes of PES48H12AG2 resets. The first is a switch fundamental reset which is the reset used to initialize the entire device. The second class is referred to as partition resets. This class has multiple sub-categories. Partition resets are associated with a specific PES48H12AG2 switch partition and corresponds to those resets defined in the PCI express base specification.
Page 74: Boot Configuration Vector
IDT Reset and Initialization Notes Registers and fields designated as Sticky (Sticky) take on their initial value as a result of the following resets. Other resets have no effect on registers and fields with this designation. – Switch Fundamental Reset –...
Page 75: Switch Fundamental Reset
IDT Reset and Initialization Notes May Be Signal Name/Description Overridden P89MERGEN Ports 8 and 9 Merge. This pin specifies whether ports 8 and 9 are merged. P1011MERGEN Ports 10 and 11 Merge. This pin specifies whether ports 10 and 11 are merged. RSTHALT Reset Halt.
Page 76 IDT Reset and Initialization Notes 10. If the sampled Switch Mode (SWMODE[3:0]) state corresponds to a mode that supports serial EEPROM initialization, then the contents of the serial EEPROM are read and appropriate switch registers are updated. – While the contents of the EEPROM are read, the switch responds to all configuration request with configuration-request-retry-status completion.
Page 77 IDT Reset and Initialization Notes The operation of a switch fundamental reset with serial EEPROM initialization is illustrated in Figure 5.1. Stable Stable Power GCLK GCLK* > 100ns PERSTN < 100 ms ~285 s ~2 s PLL Reset & Lock Link Ready SerDes CDR Lock...
Page 78: Switch Mode Dependent Initialization
IDT Reset and Initialization Switch Mode Dependent Initialization Notes Switch modes may be subdivided into normal switch modes and test modes. The modes listed below are normal switch modes. All other switch modes are test modes. – Single partition – Single partition with Serial EEPROM initialization –...
Page 79: Port Merging
IDT Reset and Initialization Notes Single Partition with Port 0 Upstream Port (Port 2 disabled) In single partition with port 0 upstream port, the initial values outlined in Table 5.3 result in the following configuration. – All switch ports, except port 2, are members of partition zero. –...
Page 80: Partition Resets
IDT Reset and Initialization Notes – All registers associated with the port remain accessible from the global address space. – The port remains in this state regardless of the setting of the port’s operating mode (i.e., via the port’s SWPORTxCTL register). An active port behaves as described throughout the rest of this specification and may be configured in one of several operating modes, as described in Chapter 6, Switch Partitions.
Page 81: Partition Hot Reset
IDT Reset and Initialization Partition Hot Reset Notes A partition hot reset is initiated by any of the following events: – Reception of TS1 ordered-sets on the partition’s upstream port indicating a hot reset. – Data link layer of the partition’s upstream port transitions to the DL_Down state. –...
Page 82: Partition Downstream Secondary Bus Reset
IDT Reset and Initialization Notes When an Upstream Secondary Bus Reset occurs, the following sequence of actions take place on logic associated with the affected partition. 1. Each downstream port whose link is up propagates the reset by transmitting TS1 ordered sets with the hot reset bit set.
Page 83: Switch Partitions
Chapter 6 Switch Partitions ® Introduction Notes The PES48H12AG2 supports up to 12 active switch partitions. Each switch partition represents an inde- pendent PCI Express hierarchy whose operation is independent of other switch partitions. A port may be configured to operate in one of four modes. –...
Page 84: Partition State
IDT Switch Partitions Notes A partition with one upstream port and no downstream ports has the following behavior. – All received requests, except configuration requests that target the upstream port, are treated as unsupported requests. – All received completions are treated as unsupported requests. –...
Page 85: Partition State Change
IDT Switch Partitions Notes The partition fundamental reset condition is considered to persist as long as the STATE field in the SWPARTxCTL register remains in the fundamental reset state. Transitioning a partition from the funda- mental reset state to the active state requires that the system meet the requirements associated with a conventional reset outlined in Section 6.6.1 in the PCIe Base specification.
Page 86: Switch Ports
IDT Switch Partitions Notes Refer to section Static Reconfiguration on page 6-15 for a sample partition and port configuration sequence programmed via the serial EEPROM. Partition State Change via Other Methods When modifying the state of a partition via methods other than EEPROM loading (i.e., via PCI Express configuration requests or using the SMBus slave), the following requirements and restrictions apply: –...
Page 87 IDT Switch Partitions Notes A port in the disabled mode has the following behavior. – All output signals associated with the port are placed in a negated state (e.g., link status and hot- plug signals). • The negated value of HPxAIN, HPxILOCKP, HPxPEP, HPxPIN, and HPxRSTN is determined as shown in Table 10.2.
Page 88 IDT Switch Partitions Notes All input signals associated with the port, except the SerDes, are ignored and have no effect on the operation of the device. – Boot configuration vector signals are sampled during a switch fundamental reset and thus their dynamic state has no effect on the operating mode of the port in any port mode.
Page 89: Port Operating Mode Change
IDT Switch Partitions Notes A port in the upstream switch port mode has the following behavior. – Has the behavior of an upstream switch port defined by the PCI express base specification. – The LTSSM is operational and behaves as an upstream port. Downstream Switch Port A port in downstream switch port mode behaves as the downstream port of a switch partition.
Page 90 IDT Switch Partitions Notes Changing the operating mode of a port is subject to the requirements and restrictions listed in the sub- sections below. Since an operating mode change may take a significant amount of time to complete, status bits are provided to indicate when the change has started and when it has completed. –...
Page 91: Common Operating Mode Change Behavior
IDT Switch Partitions Notes – The operating mode of a port in upstream switch port mode can’t be later modified to downstream switch port mode, except after a switch fundamental reset. This restriction holds even if the modi- fication from upstream switch port mode to downstream switch port mode goes through interme- diate states (e.g., unattached, disabled).
Page 92 IDT Switch Partitions Notes When a port operating mode change is initiated, the operation logically executes in the following order. 1. The OMCI bit in the SWPORTxSTS register is set. 2. The effect on the source partition, if appropriate, takes place (i.e., cleanly remove the port from the partition).
Page 93 IDT Switch Partitions Notes Upstream port removal: – A switch partition must initiate an exit from L0s on the transmitters of all downstream ports asso- ciated with the partition if it detects an exit from L0s on the receiver of its upstream port. –...
Page 94 IDT Switch Partitions Notes described in section Partition Hot Reset on page 5-9. An upstream port whose link transition to the Detect state (i.e., DL_Down) as a result of the operating mode change may trigger a hot-reset in the destination partition as described in section Partition Hot Reset on page 5-9.
Page 95 IDT Switch Partitions Notes Upstream port addition: – A switch partition must initiate an exit from L0s on the transmitters of all downstream ports asso- ciated with the partition if it detects an exit from L0s on the receiver of its upstream port. See the PCI Express Base specification for details.
Page 96: No Action Mode Change Behavior
IDT Switch Partitions Notes INTx Interrupt Signaling Adding an upstream port to a partition causes the upstream port to adopt the aggregated interrupt state of the downstream ports associated with the destination partition. This may result in the generation of Assert_INTx and Deassert_INTx messages if the new aggregated state is different from that previously reported to the root.
Page 97: Hot Reset Mode Change Behavior
IDT Switch Partitions Hot Reset Mode Change Behavior Notes Modifying the operating mode of a port when the OMA field is set to hot reset has the following behavior in addition to that specified by the common operating mode change behavior. –...
Page 98: Dynamic Reconfiguration
IDT Switch Partitions Notes – Change the port operating mode by setting the following fields in the SWPORTxCTL register. This causes the port to be added to the selected partition. • MODE field to ‘Downstream switch port’ • PART field to the appropriate partition (e.g., 0 or 1) •...
Page 99 IDT Switch Partitions Notes A system may require software notification when a partition reconfiguration occurs. If the reconfiguration results in the addition, removal, or change in operating mode of the upstream port associated with the parti- tion, then the system may be notified of the reconfiguration by a link down event detected by the component upstream of the partition (i.e., the root or switch downstream port).
Page 100 IDT Switch Partitions Notes PES48H12AG2 User Manual 6 - 18 April 5, 2013...
Page 101: Link Operation
Chapter 7 Link Operation ® Introduction Notes Link operation in the PES48H12AG2 adheres to the PCI Express 2.0 Base Specification, supporting speeds of 2.5 GT/s and 5.0 GT/s. The PES48H12AG2 contains sixteen x4 ports which may be merged in pairs to form x8 ports. The default link width of each port is x4 and the SerDes lanes are statically assigned to a port.
Page 102 IDT Link Operation Notes PExRP[0] lane 0 PExRP[0] lane 3 PExRP[1] lane 1 PExRP[1] lane 2 PES48H12AG2 PES48H12AG2 PExRP[2] lane 2 PExRP[2] lane 1 PExRP[3] lane 3 PExRP[3] lane 0 (a) x4 Port without lane reversal (b) x4 Port with lane reversal PExRP[0] lane 0 PExRP[0]...
Page 103 IDT Link Operation Notes PExRP[0] lane 1 PExRP[0] lane 0 PExRP[1] lane 0 PExRP[1] lane 1 PExRP[2] PExRP[2] PExRP[3] PExRP[3] PES48H12AG2 PES48H12AG2 PExRP[4] PExRP[4] PExRP[5] PExRP[5] PExRP[6] PExRP[6] PExRP[7] PExRP[7] (b) x2 Port with lane reversal (a) x2 Port without lane reversal PExRP[0] PExRP[0] lane 0...
Page 104 IDT Link Operation Notes PExRP[0] lane 3 PExRP[0] lane 0 PExRP[1] lane 2 PExRP[1] lane 1 PExRP[2] lane 1 PExRP[2] lane 2 PExRP[3] lane 0 PExRP[3] lane 3 PES48H12AG2 PES48H12AG2 PExRP[4] PExRP[4] PExRP[5] PExRP[5] PExRP[6] PExRP[6] PExRP[7] PExRP[7] (b) x4 Port with lane reversal (a) x4 Port without lane reversal PExRP[0] PExRP[0]...
Page 105: Link Width Negotiation
IDT Link Operation Notes PExRP[0] lane 7 PExRP[0] lane 0 PExRP[1] lane 6 PExRP[1] lane 1 PExRP[2] lane 5 PExRP[2] lane 2 PExRP[3] lane 4 PExRP[3] lane 3 PES48H12AG2 PES48H12AG2 PExRP[4] lane 3 PExRP[4] lane 4 PExRP[5] lane 2 PExRP[5] lane 5 PExRP[6] lane 1...
Page 106: Link Width Negotiation In The Presence Of Bad Lanes
IDT Link Operation Notes The actual link width is determined dynamically during link training. Ports limited to a maximum link width of x8 are capable of negotiating to a x8, x4, x2, or x1 link width. The current negotiated width of a link may be determined from the Negotiated Link Width (NLW) field in the corresponding port’s PCI Express Link Status (PCIELSTS) register.
Page 107: Link Speed Negotiation In The Pes48H12Ag2
IDT Link Operation Notes A component advertises its supported speeds via the Data Rate Identifier bits in the TS1 and TS2 training sets transmitted to its link partner during link training. The PCIe spec permits a component to change its supported speeds dynamically. It is allowed for a component to advertise supported link speeds without necessarily changing the link speed, via the Recovery LTSSM state.
Page 108: Software Management Of Link Speed
IDT Link Operation Notes The current link speed of each port is reported via the Current Link Speed (CLS) field of the port’s Link Status Register (PCIELSTS). The above behavior applies after full link retrain (i.e., when the LTSSM transi- tions through the ‘Detect’...
Page 109: Link Retraining
IDT Link Operation Notes As mentioned above, the Target Link Speed (TLS) field of the port’s Link Control 2 Register (PCIELCTL2) sets the preferred link speed. By default, the Target Link Speed of each PES48H12AG2 port is set to 5.0 GT/s. During normal operation, the link speed of a downstream port may be modified by setting the TLS field of the port’s PCIELCTL2 register to the desired speed and initiating link retraining by writing a one to the Link Retrain (LRET) bit in the Link Control (PCIELCTL) register.
Page 110: Link Down
IDT Link Operation Link Down Notes When an upstream port’s link goes down, it triggers a hot reset in the partition associated with the port, as described in section Partition Hot Reset on page 5-9. In addition: – All TLPs queued in the port’s ingress frame buffer (IFB) are silently discarded. –...
Page 111: Link States
IDT Link Operation Link States Notes PES48H12AG2 ports support the following link states: – L0 Fully operational link state – L0s Automatically entered low power state with shortest exit latency – L1 Lower power state than L0s May be automatically entered or directed by software by placing the device in the D3 state –...
Page 112: L0S Aspm
IDT Link Operation L0s ASPM Notes L0s entry/exit operates independently for each direction of the link. On the receive side, the PES48H12AG2 upstream and downstream ports always respond to L0s entry/exit requests from the link partner. On the transmit side, the L0s entry conditions must be met for 7 µs before the hardware transitions the transmit link to the L0s state.
Page 113: L1 Aspm Entry Rejection Timer
IDT Link Operation Notes L1 state from its link partner. If the link partner acknowledges the transition, then the L1 state is entered. Otherwise, L0s entry is attempted A port configured in ‘Upstream Switch Port’ mode initiates L1 entry when all of the conditions listed below are met: –...
Page 114: Link Status
IDT Link Operation Notes Some endpoint devices do not meet the required 10 µs gap between consecutive L1 ASPM entry requests. A live-lock situation can develop in the following scenario: – The Endpoint sends continuous PM_Active_State_Request_L1 DLLPs to the downstream port of a switch.
Page 115: Crosslink
IDT Link Operation Notes During normal operation (i.e, not polling.compliance), de-emphasis selection is done during the Recovery state. The downstream component of the link (i.e., switch upstream port or endpoint) advertises its desired de-emphasis by transmission of training sets. The upstream component of the link (i.e., switch downstream port or root-complex port) notes its link partner desired de-emphasis, and makes a decision about the de-emphasis to be used in the link.
Page 116: Hot Reset Operation On A Crosslink
IDT Link Operation Hot Reset Operation on a Crosslink Notes When a PES48H12AG2 port forms a crosslink, hot reset operates as follows. – For a port operating in downstream switch port mode: • Regardless of the physical layer’s mode of operation (i.e., upstream or downstream lanes), the physical layer responds to the reception of training sets with the hot reset bit set by transitioning to the hot reset state as specified in the PCI Express Base Specification.
Page 117: Table 7.2 Gen1 Compatibility Mode: Bits Cleared In Training Sets
IDT Link Operation Notes When a PES48H12AG2 port operates in Gen1 Compatibility Mode, the PHY does not set the following bits in Table 7.2 in the training sets that it transmits. PCIe 1.1 and Training Symbol earlier PCI Express 2.0 Definition Definition Reserved 5.0 GT/s Data Rate Support...
Page 118 IDT Link Operation Notes PES48H12AG2 User Manual 7 - 18 April 5, 2013...
Page 119: Serdes
Chapter 8 SerDes ® Introduction Notes This chapter describes the controllability of the Serialiazer-Deserializer (SerDes) block associated with each PES48H12AG2 port. A SerDes block is composed of the serializing/deserializing logic for four PCI Express lanes (i.e., a SerDes “quad”), plus a central block that controls the quad as a whole. This central block is called CMU, and contains functionality such as a PLL to generate a high-speed clock used by each lane, initialization of the quad, etc.
Page 120: De-Emphasis
IDT SerDes Notes In addition to this, the PES48H12AG2 offers proprietary fine grain controllability of the SerDes trans- mitter voltage level, across a wide range of settings. The PES48H12AG2 places no restrictions on the time at which these settings can be modified (e.g., they can be modified during normal operation of the link or while the link is being tested).
Page 121: Receiver Equalization
IDT SerDes Notes tion, signal de-emphasis is turned off. Low-swing mode is a per-link feature, meaning that all lanes of the port operate low-swing simultaneously. Refer to section Low-Swing Transmitter Voltage Mode on page 8-13 for details on enabling low-swing mode on a port. Receiver Equalization In addition to the transmitter controls described above, the PES48H12AG2 SerDes also contains a receiver equalizer to compensate for effects of channel loss on received signal (i.e., high-speed signal...
Page 122: Serdes Transmitter Control Registers
IDT SerDes Notes When the Transmit Margin (TM) field in the port’s PCIELCTL2 register is set to ‘Normal Operating Range’, the transmitter voltage level for each SerDes lane of the port is controlled via the S[x]TXLCTL0 and S[x]TXLCTL1 registers. Otherwise, the TM field controls the SerDes voltage directly for all SerDes lanes of the port.
Page 123: Table 8.1 Serdes Transmit Level Controls In The S[X]Txlctl0 And S[X]Txlctl1 Registers
IDT SerDes Notes Relevant fields in Relevant fields in PHY Operation Mode S[x]TXLCTL0 S[x]TXLCTL1 Coarse De- emphasis Slew Rate Voltage Data Drive Level / Fine-De- Control & Control Swing Rate emphasis emphasis Control Transmitter (Course & Fine) Equalization Full-Swing 2.5 GT/s -3.5 dB CDC_FS3DBG1 TX_SLEW_G1 &...
Page 124: Table 8.2 Serdes Transmit Driver Settings In Gen1 Mode
IDT SerDes Notes Settings of Relevant Fields in the S[x]TXLCTL0 & Transmit Levels S[x]TXLCTL1 registers Drive empha- TDVL_ TX_EQ_ CDC_ FDC_ TX_SLEW empha- Level sized FS3DBG1 3DBG1 FS3DBG1 FS3DBG1 Level -3.6 0x1C -3.6 0x1B -3.6 0x1A -3.6 0x19 -3.6 0x18 -3.5 0x17 -3.5...
Page 125: Table 8.3 Serdes Transmit Driver Settings In Gen2 Mode With -3.5Db De-Emphasis
IDT SerDes Notes Settings of Relevant Fields in the S[x]TXLCTL0 & Transmit Levels S[x]TXLCTL1 registers Drive emphas TDVL_ TX_EQ_ CDC_ FDC_ TX_SLEW emphas Level ized FS3DBG2 3DBG2 FS3DBG2 FS3DBG2 Level -3.5 0x1C -3.5 0x1B -3.5 0x1A -3.6 0x19 -3.6 0x18 -3.6 0x17 -3.7...
Page 126: Table 8.4 Serdes Transmit Driver Settings In Gen2 Mode With -6.0Db De-Emphasis
IDT SerDes Notes Table 8.4 shows a number of possible settings for the drive, de-emphasis, and slew rate controls in Gen2 mode with -6.0dB de-emphasis. The default setting is highlighted. As mentioned above, the PCI Express 2.0 spec allows an error of up to +/- 0.5dB on the de-emphasis. All settings listed in the table ensure that the de-emphasis is kept within the allowable range.
Page 127 IDT SerDes Notes Settings of Relevant Fields in the Transmit Levels S[x]TXLCTL0 & S[x]TXLCTL1 registers Drive empha- TDVL_ TX_EQ_ CDC_ FDC_ TX_SLEW empha- Level sized FS6DBG2 6DBG2 FS6DBG2 FS6DBG2 Level -6.0 0x03 -6.1 0x02 -6.2 0x01 -6.3 0x00 Table 8.4 SerDes Transmit Driver Settings in Gen2 Mode with -6.0dB de-emphasis (Part 2 of 2) When the PHY operates in low-swing mode, de-emphasis is automatically turned off.
Page 128 IDT SerDes Notes When the PHY operates in Gen2 data rate with -6.0 dB de-emphasis, the fine de-emphasis control (FDC_FS6DBG2 field in the S[x]TXLCTL1 register) has the effect shown in Figure 8.3. In the figure, TXLEV[4:0] refers to the TDVL_FS6DBG2 field in the S[x]TXLCTL1 register. As shown in these figures, the de-emphasis applied on the line varies depending on the setting of the transmit drive level field.
Page 129: Table 8.5 Transmitter Slew Rate Settings
IDT SerDes Notes Figure 8.3 De-emphasis Applied on Link as a Function of the Fine de-emphasis and Transmit Drive Level Controls, when the PHY Operates in Gen1 Data Rate with -6.0 dB Nominal de-emphasis Finally, note that it is possible to turn off de-emphasis (i.e., 0 dB de-emphasis) for a given PHY operating mode by setting the corresponding transmitter equalization control to 0x0, the coarse de-emphasis control to a value of 0x3, and the fine de-emphasis control to a value of 0x7.
Page 130: Transmit Margining Using The Pci Express Link Control 2 Register
IDT SerDes Notes Table 8.5 Transmitter Slew Rate Settings (Part 2 of 2) Transmit Margining Using the PCI Express Link Control 2 Register When the Transmit Margin (TM) field in the port’s PCIELCTL2 register is set to a value other than ‘Normal Operating Range’, the transmitter voltage levels are controlled by hardware based on the setting of the TM field, and not by the S[x]TXLCTL0 and S[x]TXLCTL1 registers.
Page 131: Low-Swing Transmitter Voltage Mode
IDT SerDes Notes Finally, when the TM field is modified, the newly selected value is not applied until the PHY LTSSM tran- sitions through the states in which it is allowed to modify the transmit margin setting on the line (e.g., Recovery.RcvrLock).
Page 132: Receiver Equalization Controls
IDT SerDes Notes Drive Level TDVL_LSG2 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 Table 8.8 SerDes Transmit Drive Swing in Low Swing Mode at Gen2 Speed When the PHY enters the Polling.Compliance state and low-swing mode is enabled, the following occurs: –...
Page 133: Serdes Power Management
IDT SerDes SerDes Power Management Notes In order to maximize power savings in the SerDes, the PES48H12AG2 adheres to the following guide- lines. For SerDes quads that are used, their power state depends on the state of the port(s) associated with the SerDes, as described below.
Page 134 IDT SerDes Notes PES48H12AG2 User Manual 8 - 16 April 5, 2013...
Page 135: Theory Of Operation
Chapter 9 Theory of Operation ® Introduction Notes Each PES48H12AG2 partition operates logically as a completely independent PCI Express switch that implements the behavior and capabilities required of a switch by the PCI Express Base 2.0 specification. This chapter describes the PES48H12AG2-specific architectural behavior for the PCI Express switch asso- ciated with each partition.
Page 136: Downstream Port Interrupts
IDT Theory of Operation Notes It follows that MSIs generated by the switch’s ports can’t fall within the multicast BAR aperture in the partition. When this occurs, the behavior is undefined. EN bit in INTXD bit Unmasked MSICAP in PCICMD Action Interrupt Register...
Page 137: Access Control Services
IDT Theory of Operation Notes Upstream Port Interrupt (Port 0) INTA INTB INTC INTD Device (N mod 4) = Device (N mod 4) = Device (N mod 4) = Device (N mod 4) = 0 INTA 0 INTB 0 INTC 0 INTD Device (N mod 4) = Device (N mod 4) =...
Page 138 IDT Theory of Operation Notes Upstream Port TLP route Completion with Bridge completer-abort status Partition 1 – Virtual PCI Bus ACS Source Validation (TLP is dropped at this point) Bridge Bridge Downstream Ports Figure 9.1 ACS Source Validation Example Figure 9.2 shows an example of ACS peer-to-peer request re-direct at a downstream port. In this case, the offending TLP received by the downstream port is re-directed towards the root-complex.
Page 139: Table 9.4 Prioritization Of Acs Checks For Request Tlps
IDT Theory of Operation Notes Upstream Port Intended TLP Route ACS Re-directed Route Bridge Partition 1 – Virtual PCI Bus ACS Upstream Forwarding Bridge Bridge Downstream Ports Figure 9.3 ACS Upstream Forwarding Example When multiple ACS checks are enabled, they are prioritized as described below. Table 9.4 shows the prioritization for ACS checks associated with the reception of request TLPs.
Page 140: Error Detection And Handling
IDT Theory of Operation Notes ACS Check Priority Comment ACS Upstream For- 2 (Highest) Applicable to request or completion TLPs warding received by the downstream port on its ingress link that target the port’s egress link. This is not considered a peer-to-peer transfer. ACS Peer-to-Peer 1 (Lowest) Applicable to non-relaxed-ordered peer-to-peer...
Page 141: Physical Layer Errors
IDT Theory of Operation Notes A PCI-to-PCI Bridge function claims a TLP in the following cases: – Address Routed TLPs: If received on the primary side of the bridge, the TLPs address falls within the address space range(s) programmed in the base/limit registers. If received on the secondary side of the bridge, always.
Page 142: Transaction Layer Errors
IDT Theory of Operation Notes A DL protocol error occurs when an ACK or NAK DLLP is received and the sequence number specified by AckNak_Seq does not correspond to an unacknowledged TLP or to the value in ACKD_SEQ Transaction Layer Errors Table 9.9 lists non-ACS error checks associated with a PCI-to-PCI bridge function and the action taken when an error is detected.
Page 143: Table 9.9 Transaction Layer Errors Associated With The Pci-To-Pci Bridge Function
IDT Theory of Operation Notes Role Func- Based Express Error tion- (Advisory) Specifica- Action Taken Condition Specific Error tion Error Reporting Section Condition Poisoned TLP 2.7.2.2 Advisory when Detected Parity Error (DPE) bit in the received the correspond- PCISTS or SECSTS register set appro- ing error is con- priately.
Page 144 IDT Theory of Operation Notes Role Func- Based Express Error tion- (Advisory) Specifica- Action Taken Condition Specific Error tion Error Reporting Section Condition Unexpected com- 2.3.2 Yes if a func- Advisory when Non-advisory cases: uncorrectable pletion received tion claims the correspond- error processing.
Page 145: Table 9.10 Conditions Handled As Unsupported Requests (Ur) By The Pci-To-Pci Bridge Function
IDT Theory of Operation Notes PCIe Specifica- Conditions handled as UR Description tion Section Routing Errors Refer to section Routing Errors on page 9-16. Numerous Vendor Defined Type 0 message recep- Vendor Defined Type 0 message which targets the 2.2.8.6 tion PCI-to-PCI bridge function.
Page 146: Table 9.12 Egress Malformed Tlp Error Checks
IDT Theory of Operation Notes TLP Type Error Check Message Requests TC = 0 interrupt message Power management message Error signalling message Unlock message Set power limit message TLPs with Route to Root Complex routing. May only be received on downstream ports TLPs with Broadcast from Root Complex rout- May only be received on upstream ports ing.
Page 147: Table 9.13 Acs Violations For Ports Operating In Downstream Switch Port Mode
IDT Theory of Operation Notes Role Based Express (Advisory) ACS Check Specifica- Error Action Taken tion Reporting Section Condition ACS Source Validation 6.12.1.1 Advisory when If TLP is a non-posted request, a completion the correspond- with ‘completer abort’ status is generated. Note ing error is con- that this is not considered a completer abort figured as non-...
Page 148: Table 9.14 Prioritization Of Transaction Layer Errors
IDT Theory of Operation Notes In addition, the Detected Parity Error bit (DPE) in the PCISTS and SECSTS registers is not subject to error pollution rules and is therefore set when the PCI-to-PCI bridge receives a poisoned TLP on its primary or secondary side respectively, even if error pollution rules indicate that the poisoned TLP received error is superseded by a higher priority error.
Page 149: Table 10.1 Table
IDT Theory of Operation Notes TLP Received by Done Function Handle per Table 12.9 Receiver Overflow Error? Handle per Table 12.9 ECRC TLP Dropped? Error? If ECRC error detected, handle per Table 12.9 but do not log Malformed error; Else, Malformed TLP? handle per Table 12.9 If ECRC detected, handle per Table 12.13...
Page 150: Routing Errors
IDT Theory of Operation Notes Note the following: – Except for ECRC and Poisoned TLP errors, all other errors detected on the received TLP cause the detecting function to consume, drop, or nullify the TLP. – Receiver overflow errors are only checked and logged. –...
Page 151: Bus Locking
IDT Theory of Operation Notes Address Routed TLPs TLPs received by an upstream port that match the upstream port’s address range but which do not match a downstream port’s address range within the partition (i.e., TLPs that do not route through the parti- tion).
Page 152 IDT Theory of Operation Notes A locked transaction sequence is requested by the root complex by issuing a Memory Read Request - Locked (MRdLk) transaction. A lock is established when a lock request is successfully completed with a Completion with Data - Locked (CplDLk). A lock is released with an Unlock message (Msg) sent by the root complex.
Page 153 IDT Theory of Operation Notes Note that when a TLP received by port is blocked from being forwarded due to a bus-locked partition, the TLP is delayed until the partition is unlocked. If the partition is locked for an extended period, this may cause TLPs to be discarded due to switch time-outs.
Page 154 IDT Theory of Operation Notes PES48H12AG2 User Manual 9 - 20 April 5, 2013...
Page 155: Hot-Plug And Hot-Swap
Chapter 10 Hot-Plug and Hot-Swap ® Introduction Notes As illustrated in Figures 10.1 through 10.3, a PCIe switch may be used in one of three hot-plug configu- rations. Figure 10.1 illustrates the use of PES48H12AG2 in an application in which two downstream ports are connected to slots into which add-in cards may be hot-plugged.
Page 156 IDT Hot-Plug and Hot-Swap Notes Upstream Link Add-In Card Port 0 PES48H12AG2 Port x Port y PCI Express PCI Express Device Device Figure 10.2 Hot-Plug with Switch on Add-In Card Application Upstream Link Carrier Card Port 0 PES48H12AG2 Master SMBus Port x Port y SMBus I/O...
Page 157: Hot-Plug Signals
IDT Hot-Plug and Hot-Swap Notes Associated with all PES48H12AG2 ports is a hot-plug controller. However, hot-plug is only supported when a port is configured to operate in downstream switch port mode. Hot-plug is supported within switch partitions. When hot-plug is enabled in a downstream port of a switch partition, the behavior is identical do that expected if the switch partition were a stand-alone PCIe switch.
Page 158 IDT Hot-Plug and Hot-Swap Notes – When the Hot-Plug GPIO Port Map (HPxGPIOPRT) field in the Hot-Plug GPIO Signal Map (HPSIGMAP) register selects an invalid port (i.e., no port or a port that does not exist in the switch), hot-plug GPIO alternate function signal output pin values are equal to their unused value as defined below.
Page 159: Port Reset Outputs
IDT Hot-Plug and Hot-Swap Notes When the MRL Automatic Power Off (MRLPWROFF) bit is set in the HPCFGCTL register and the Manual Retention Latch Sensor Present (MRLP) bit is set in the PCI Express Slot Capability (PCIESCAP) register, then power to the slot is automatically turned off when the MRL sensor indicates that the MRL is open.
Page 160: Hot-Plug Events
IDT Hot-Plug and Hot-Swap Notes While slot power is disabled, the corresponding downstream port reset output is asserted. When slot power is enabled by writing a zero to the PCC bit, the Port x Power Enable Output (PxPEP) is asserted and then power to the slot is enabled and the corresponding downstream port reset output is negated.
Page 161: Legacy System Hot-Plug Support
IDT Hot-Plug and Hot-Swap Notes the PCI Express Slot Control (PCIESCTL) register or by the HPIE bit: the Attention Button Pressed (ABP), Power Fault Detected (PFD), MRL Sensor Changed (MRLSC), Presence Detected Changed (PDC), Command Completed (CC), and Data Link Layer Active State Change (DLLASC). When an unmasked hot-plug interrupt is generated, the action taken is determined by the MSI Enable (EN) bit in the MSI Capability (MSICAP) register and the Interrupt Disable (INTXD) bit in the PCI Command (PCICMD) register.
Page 162: Hot-Swap
IDT Hot-Plug and Hot-Swap Notes General Purpose Event Enable General Purpose Event Mechanism Interrupt Slot Control Disable Register Activate INTx Hot-Plug Interrupt Mechanism Enable Slot Status Register Activate MSI Mechanism Command Completed Enable Command Completed MSI Enable RW1C RW1C Attention Button Pressed Enable Attention Button Pressed...
Page 163: Power Management
Chapter 11 Power Management ® Introduction Notes Located in configuration space of each Function in the PES48H12AG2 (i.e., PCI-to-PCI Bridge Func- tion) is a power management capability structure. PES48H12AG2 Functions support the following device power management states: – D0 (D0 and D0 uninitialized active...
Page 164: Table 11.1 Pes48H12Ag2 Power Management State Transition Diagram
IDT Power Management Notes Partition Reset Uninitialized Active cold Figure 11.1 PES48H12AG2 Power Management State Transition Diagram From State To State Description D0 Uninitialized Partition reset (any type). D0 Uninitialized D0 Active Function configured by software D0 Active The Power Management State (PMSTATE) field in the PCI Power Management Control and Status (PMCSR) register is written with the value that corresponds to the D3 state.
Page 165: Pme Messages
IDT Power Management Notes • This requires transitioning the link to the L0 state when the completion needs to be transmitted on the link by the bridge Function and the link is not in L0. – All request TLPs received on the secondary interface are treated as unsupported requests (UR). PME Messages PES48H12AG2 does not support generation of PME messages from the D3 state.
Page 166: Power Budgeting Capability
IDT Power Management Power Budgeting Capability Notes PES48H12AG2 contains the mechanisms necessary to implement the PCI-Express power budgeting enhanced capability. However, by default, these mechanisms are not enabled. To enable the power budgeting capability, registers in this capability should be initialized and the Next Pointer (NXTPTR) field in one of the other enhanced capabilities should be initialized to point to the power budgeting capability.
Page 167: General Purpose I/O
Chapter 12 General Purpose I/O ® Introduction Notes The PES48H12AG2 has 54 General Purpose I/O (GPIO) pins that may be individually configured as: general purpose inputs, general purpose outputs, or alternate functions. GPIO pins are controlled by the General Purpose I/O Function [1:0] (GPIOFUNCx), General Purpose I/O Configuration [1:0] (GPIOCFGx), General Purpose I/O Data [1:0] (GPIODx), and General Purpose I/O Alternate Function Select [1:0] (GPIO- AFSELx) registers.
Page 168: Table 12.2 General Purpose I/O Pin Alternate Function
IDT General Purpose I/O Notes GPIO Pin Alternate Function 0 Alternate Function 1 PART0PERSTN — PART1PERSTN — PART2PERSTN — PART3PERSTN — — P0LINKUPN GPEN P0ACTIVEN — — — — IOEXPINTN — HP0APN — HP0PDN — HP0PFN — HP0PWRGDN — HP0MRLN —...
Page 169: Table 12.3 Gpio Alternate Function Pins
IDT General Purpose I/O Notes GPIO Pin Alternate Function 0 Alternate Function 1 HP3APN P8LINKUPN HP3PDN P8ACTIVEN HP3PFN P9LINKUPN HP3PWRGDN P9ACTIVEN HP3MRLN P10LINKUPN HP3AIN P10ACTIVEN HP3PIN P11LINKUPN HP3PEP P11ACTIVEN HP3RSTN — HP4APN — HP4PDN — HP4PFN — HP4PWRGDN — HP4MRLN —...
Page 170 IDT General Purpose I/O Notes Signal Type Name/Description PARTxPERSTN Partition x Fundamental Reset. Assertion of this signal initiates a partition fundamental reset in the corresponding partition. PxACTIVEN Port x Link active status output. PxLINKUPN Port x link up status output. Table 12.3 GPIO Alternate Function Pins (Part 2 of 2) When configured as an alternate function in the GPIOFUNCx register, a pin behaves as the alternate function signal selected by the GPIOAFSEL register.
Page 171: Smbus Interfaces
Chapter 13 SMBus Interfaces ® Introduction Notes PES48H12AG2 has two SMBus interfaces. The slave SMBus interface provides full access to all soft- ware visible registers, allowing every register in the device to be read or written by an external SMBus master.
Page 172: Serial Eeprom
IDT SMBus Interfaces Serial EEPROM Notes During a switch fundamental reset, an optional serial EEPROM may be used to initialize any software visible register in the device. Serial EEPROM loading occurs if the Switch Mode (SWMODE) signal selects an operating mode that performs serial EEPROM initialization. The address used by the SMBus interface to access the serial EEPROM is specified by the MSMBADDR[4:1] signals as shown in Table 13.1.
Page 173: Figure 13.2 Single Double Word Initialization Sequence Format
IDT SMBus Interfaces Notes A blank serial EEPROM contains 0xFF in all data bytes. When the PES48H12AG2 is configured to initialize from serial EEPROM and the first 256 bytes read from the EEPROM all contain the value 0xFF, then loading of the serial EEPROM is aborted, the computed checksum is ignored, the Blank Serial EEPROM (BLANK) bit is set in the SMBus Status (SMBUSSTS) register, and normal device operation begins (i.e., the device operates in the same manner as though it were not configured to initialize from the serial EEPROM).
Page 174: Figure 13.3 Sequential Double Word Initialization Sequence Format
IDT SMBus Interfaces Notes TYPE Reserved Byte 0 (must be zero) Byte 1 SYSADDR9:2] Byte 2 SYSADDR[18:10] Byte 3 NUMDW[7:0] Byte 4 NUMDW[15:8] Byte 5 DATA0[7:0] Byte 6 DATA0[15:8] Byte 7 DATA0[23:16] Byte 8 DATA0[31:24] Byte 4n+5 DATAn[7:0] Byte 4n+ 6 DATAn[15:8] Byte 4n+7 DATAn[23:16]...
Page 175: Programming The Serial Eeprom
IDT SMBus Interfaces Notes The checksum is verified in the following manner. An 8-bit counter is cleared and the 8-bit sum is computed over the bytes read from the serial EEPROM, including the entire contents of the configuration done sequence. The correct result should always be 0xFF (i.e., all ones).
Page 176: I/O Expanders
IDT SMBus Interfaces Notes To write a byte to the serial EEPROM, the root should configure the ADDR field with the byte address of the serial EEPROM location to be written and set the OP field to “write.” If the serial EEPROM is not busy (i.e., the BUSY bit is cleared), then the write operation may be initiated by writing the value to be written to the DATA field.
Page 177: Table 13.5 I/O Expander Default Output Signal Value
IDT SMBus Interfaces Notes SMBus I/O Section Function Expander Lower / Upper Partition fundamental reset inputs Lower / Upper Link status Lower / Upper Link activity Table 13.4 I/O Expander Function Allocation (Part 2 of 2) During PES48H12AG2 initialization, the SMBus/I2C-bus address allocated to each I/O expander used in that system configuration should be written to the corresponding IO Expander Address (IOE[13:0]ADDR) field.
Page 178 IDT SMBus Interfaces Notes The following I/O expander configuration sequence is issued by PES48H12AG2 to I/O expanders 0 through 7, 9 and 10 (i.e., the ones that contain general port hot-plug signals and electromechanical interlock signals). – Write the default value of the outputs bits on the lower eight I/O expander pins (i.e., I/O-0.0 through I/O-0.7) to I/O expander register 2.
Page 179 IDT SMBus Interfaces Notes PES48H12AG2 has one combined I/O expander interrupt input, labeled IOEXPINTN, which is a GPIO alternate function. Associated with each I/O expander is an open drain interrupt output that is asserted when an I/O expander input pin changes state. The open drain I/O expander interrupt output of all I/O expanders should be tied together on the board and connected to the appropriate GPIO.
Page 180: Table 13.7 Pin Mapping I/O Expander 8
IDT SMBus Interfaces Notes SMBus I/O Expander Type Signal Description 3 (I/O-0.3) PxPWRGDN Port x power good input 4 (I/O-0.4) PxAIN Port x attention indicator output 5 (I/O-0.5) PxPIN Port x power indicator output 6 (I/O-0.6) PxPEP Port x power enable output 7 (I/O-0.7) PxRSTN Port x reset output...
Page 181 IDT SMBus Interfaces Notes SMBus I/O Expander Type Signal Description 10 (I/O-1.2) P10MRLN Port 10 manually operated retention latch (MRL) input 11 (I/O-1.3) P11MRLN Port 11 manually operated retention latch (MRL) input 12 (I/O-1.4) Unused 13 (I/O-1.5) Unused 14 (I/O-1.6) Unused 15 (I/O-1.7) Unused...
Page 182: Table 13.10 I/O Expander 11 - Partition Fundamental Reset Inputs
IDT SMBus Interfaces Notes I/O Expander 10 SMBus I/O Expander Type Signal Description 0 (I/O-0.0) P8ILOCKST Port 8 electromechanical interlock state input 1 (I/O-0.1) P9ILOCKST Port 9 electromechanical interlock state input 2 (I/O-0.2) P10ILOCKST Port 10 electromechanical interlock state input 3 (I/O-0.3) P11ILOCKST Port 11 electromechanical interlock state input...
Page 183: Table 13.11 I/O Expander 12 - Link Up Status
IDT SMBus Interfaces Notes SMBus I/O Expander Type Signal Description 11 (I/O-1.3) PART11PERSTN Partition 11 Fundamental Reset Input 12 (I/O-1.4) Unused 13 (I/O-1.5) Unused 14 (I/O-1.6) Unused 15 (I/O-1.7) Unused Table 13.10 I/O Expander 11 - Partition Fundamental Reset Inputs (Part 2 of 2) I/O-x.y corresponds to the notation used for PCA9555 port x I/O pin y.
Page 184: Slave Smbus Interface
IDT SMBus Interfaces Notes I/O Expander 13 SMBus I/O Expander Type Signal Description 0 (I/O-0.0) P0ACTIVEN Port 0 Link active status output 1 (I/O-0.1) P1ACTIVEN Port 1 Link active status output 2 (I/O-0.2) P2ACTIVEN Port 2 Link active status output 3 (I/O-0.3) P3ACTIVEN Port 3 Link active status output...
Page 185: Smbus Transactions
IDT SMBus Interfaces Notes Address Address Bit Value SSMBADDR[5] Table 13.13 Slave SMBus Address (Part 2 of 2) SMBus Transactions The slave SMBus interface responds to the following SMBus transactions initiated by an SMBus master. See the SMBus 2.0 specification for a detailed description of these transactions. –...
Page 186: Table 13.15 Csr Register Read Or Write Operation Byte Sequence
IDT SMBus Interfaces Notes The FUNCTION field in the command code indicates if the SMBus operation is a system address register read/write or a serial EEPROM read/write operation. Since the format of these transactions is different. They will be described individually in the following sections. If a command is issued while one is already in progress or if the slave is unable to supply data associated with a command, then the command is NACKed.
Page 187: Table 13.16 Csr Register Read Or Write Cmd Field Description
IDT SMBus Interfaces Notes Name Type Description Field BELL Read/Write Byte Enable Lower. When set, the byte enable for bits [7:0] of the data word is enabled. BELM Read/Write Byte Enable Lower Middle. When set, the byte enable for bits [15:8] of the data word is enabled.
Page 188: Table 13.18 Serial Eeprom Read Or Write Cmd Field Description
IDT SMBus Interfaces Notes Byte Field Description Position Name EEADDR Serial EEPROM Address. This field specifies the address of the Serial EEPROM on the Master SMBus when the USA bit is set in the CMD field. Bit zero must be zero and thus the 7-bit address must be left justified.
Page 189: Figure 13.8 Csr Register Read Using Smbus Block Write/Read Transactions With Pec Disabled
IDT SMBus Interfaces Notes Sample Slave SMBus Operation This section illustrates sample Slave SMBus operations. Shaded items are driven by PES48H12AG2’s slave SMBus interface and non-shaded items are driven by an SMBus host. PES48H12AG2 Slave CCODE BYTCNT=3 CMD=read ADDRL ADDRU SMBus Address START,END PES48H12AG2 Slave...
Page 190: Figure 13.11 Serial Eeprom Write Using Smbus Block Write Transactions With Pec Disabled
IDT SMBus Interfaces Notes PES48H12AG2 Slave CCODE BYTCNT=5 CMD=write EEADDR ADDRL SMBus Address START,END ADDRU DATA Figure 13.11 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Disabled PES48H12AG2 Slave CCODE BYTCNT=5 CMD=write EEADDR ADDRL SMBus Address START,END ADDRU DATA Figure 13.12 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Enabled PES48H12AG2 Slave...
Page 191: Multicast
Chapter 14 Multicast ® Introduction Notes The PES48H12AG2 implements multicast within switch partitions as defined by the PCI-SIG Multicast ECN. The multicast capability enables a single TLP to be forwarded to multiple destinations. The destina- tions to which a multicast TLP is forwarded are referred to as a multicast group. –...
Page 192: Figure 14.1 Multicast Group Address Ranges
IDT Multicast Notes Only posted memory write TLPs and address routed message TLPs can be multicast TLPs. The primary determinant of whether or not a memory write or address routed message TLP is a multicast TLP is its address and the address associated with multicast address regions. A multicast address region may overlap a non-multicast address region.
Page 193: Figure 14.2 Multicast Group Address Region Determination
IDT Multicast Notes The starting address of the region associated multicast group zero is equal to the multicast base address defined by the Multicast Base Address Low (MCBARL) field in the MCBARL register and the Multi- cast Base Address High (MCBARH) field in the Multicast Base Address High (MCBARH) register. –...
Page 194: Multicast Tlp Routing
IDT Multicast Notes Note that the “block all” and “block untranslated” functions are performed at the ingress port on which the multicast TLP was received. A received multicast TLP without errors is forwarded to egress ports as described in the next section. Multicast TLP Routing A multicast TLP received without error by a function is forwarded as described in this section.
Page 195 IDT Multicast Notes A side-effect of modifying the address due to multicast overlay processing is that the ECRC associated with the original TLP may not be correct for the new modified TLP. Therefore, functions perform the following ECRC processing: – If multicast overlay processing is disabled, then no ECRC processing is performed as part of multi- cast egress processing.
Page 196 IDT Multicast Notes PES48H12AG2 User Manual 14 - 6 April 5, 2013...
Page 197: Register Organization
Chapter 15 Register Organization ® Introduction Notes All software visible registers in the PES48H12AG2 are contained in a 256 KB global address space. The address of a register in this address range is referred to as the system address of the register. –...
Page 198: Partial-Byte Access To Word And Dword Registers
IDT Register Organization Notes The entire PES48H12AG2 global address space may be accessed using PCI configuration requests from any PES48H12AG2 PCI function. – Located in each PCI function is a Global Address Space Access Address (GASAADDR) and Global Address Space Access Data (GASADATA) register. –...
Page 199: Pci-To-Pci Bridge Registers
IDT Register Organization PCI-to-PCI Bridge Registers Notes This section outlines the configuration space associated with PCI-to-PCI bridges. These registers are accessible as function 0 when the port is configured in the following modes. – Upstream switch port – Downstream switch port These registers are always accessible regardless of the port mode using global address space access registers (i.e., GASAADDR and GASADATA), SMBus, or serial EEPROM.
Page 200: Table 15.2 Default Pci Capability List Linkage
IDT Register Organization Notes Default Value of PCI Capability Structure Next Pointer Field (NXTPTR) Offset in Name Configuration Space PCI Express Capability (PCIECAP) 0x040 0x0C0 0x0C0 PCI Power Management Capability (PMCAP) 0x0C0 0x0D0 Message Signaled Interrupt Capability (MSICAP) 0x0D0 Subsystem ID and Subsystem Vendor Capability 0x0F0 (SSIDSSVIDCAP) Table 15.2 Default PCI Capability List Linkage...
Page 201: Figure 15.1 Pci-To-Pci Bridge Configuration Space Organization
IDT Register Organization 0x000 PCI Configuration Space (64 Dwords) 0x000 0x100 Advanced Error Reporting Enhanced Capability 0x180 Device Serial Number Enhanced Capability Type 1 Configuration Header 0x200 PCIe Virtual Channel Enhanced Capability 0x280 Power Budgeting Enhanced Capability 0x040 0x320 PCI Express Capability Structure ACS Enhanced Capability 0x330...
Page 202: Table 15.4 Pci-To-Pci Bridge Configuration Space Registers
IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x000 Word VID - Vendor Identification Register (0x000) on page 16-1 0x002 Word DID - Device Identification Register (0x002) on page 16-1 0x004 Word PCICMD PCICMD - PCI Command Register (0x004) on page 16-1 0x006 Word PCISTS...
Page 203 IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x044 DWord PCIEDCAP PCIEDCAP - PCI Express Device Capabilities (0x044) on page 16-11 0x048 Word PCIEDCTL PCIEDCTL - PCI Express Device Control (0x048) on page 16-13 0x04A Word PCIEDSTS PCIEDSTS - PCI Express Device Status (0x04A) on page 16-14 0x04C DWord PCIELCAP...
Page 204 IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x10C Dword AERUESV AERUESV - AER Uncorrectable Error Severity (0x10C) on page 16-36 0x110 Dword AERCES AERCES - AER Correctable Error Status (0x110) on page 16-37 0x114 Dword AERCEM AERCEM - AER Correctable Error Mask (0x114) on page 16-38 0x118 Dword AERCTL...
Page 205 IDT Register Organization Notes Cfg. Register Size Register Definition Offset Mnemonic 0x30C Dword PWRBDV3 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C) on page 16-48 0x310 Dword PWRBDV4 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C) on page 16-48 0x314 Dword...
Page 206: Idt Proprietary Port Specific Registers
IDT Register Organization IDT Proprietary Port Specific Registers Notes This section outlines the address range 0x400 through 0xFFF in the PCI-to-PCI bridge address space. This address range contains IDT proprietary registers that are port specific. Registers in this address range may be accessed using PCI configuration requests to the corresponding PCI-to-PCI bridge function 0 header, global address space access registers, SMBus, or serial EEPROM.
Page 207: Table 15.5 Proprietary Port Specific Registers
IDT Register Organization Notes Cfg. Register Size Register Definition Offset Mnemonic 0x420 Dword PCIESCTLIV PCIESCTLIV - PCI Express Slot Control Initial Value (0x420) on page 16-57 0x480 DWord IERRORCTL IERRORCTL - Internal Error Reporting Control (0x480) on page 16- 0x484 DWord IERRORSTS IERRORSTS - Internal Error Reporting Status (0x484) on page 16-...
Page 208: Switch Configuration And Status Registers
IDT Register Organization Switch Configuration and Status Registers Notes This section outlines switch configuration and status registers. These registers are accessible using global address space access registers (i.e., GASAADDR and GASADATA), SMBus, or serial EEPROM. Figure 15.3 shows the organization of the address space. Registers in this address range are referenced as REGNAME where REGNAME represents the register name in Table 15.6.
Page 209: Table 15.6 Switch Configuration And Status
IDT Register Organization Notes Cfg. Register Size Register Definition Offset Mnemonic 0x0000 DWord SWCTL SWCTL - Switch Control (0x0000) on page 17-1 0x0004 DWord BCVSTS BCVSTS - Boot Configuration Vector Status (0x0004) on page 17-2 0x0008 DWord PCLKMODE PCLKMODE - Port Clocking Mode (0x0008) on page 17-3 USSBRDELAY - Upstream Secondary Bus Reset Delay (0x008C) 0x008C DWord...
Page 210 IDT Register Organization Notes Cfg. Register Size Register Definition Offset Mnemonic 0x0364 DWord SWPORT3STS SWPORT[11:0]STS - Switch Port x Status on page 17-7 0x0380 DWord SWPORT4CTL SWPORT[11:0]CTL - Switch Port x Control on page 17-6 0x0384 DWord SWPORT4STS SWPORT[11:0]STS - Switch Port x Status on page 17-7 0x03A0 DWord SWPORT5CTL...
Page 211 IDT Register Organization Notes Cfg. Register Size Register Definition Offset Mnemonic 0x0850 DWord S2RXEQLCTL S[11:0]RXEQLCTL - SerDes x Receiver Equalization Lane Control on page 17-16 0x0860 DWord S3CTL S[11:0]CTL - SerDes x Control on page 17-9 0x0864 DWord S3TXLCTL0 S[11:0]TXLCTL0 - SerDes x Transmitter Lane Control 0 on page 17- 0x0868 DWord S3TXLCTL1...
Page 212 IDT Register Organization Notes Cfg. Register Size Register Definition Offset Mnemonic 0x0910 DWord S8RXEQLCTL S[11:0]RXEQLCTL - SerDes x Receiver Equalization Lane Control on page 17-16 0x0920 DWord S9CTL S[11:0]CTL - SerDes x Control on page 17-9 0x0924 DWord S9TXLCTL0 S[11:0]TXLCTL0 - SerDes x Transmitter Lane Control 0 on page 17- 0x0928 DWord S9TXLCTL1...
Page 213 IDT Register Organization Notes Cfg. Register Size Register Definition Offset Mnemonic 0x0ABC DWord HPCFGCTL HPCFGCTL - Hot-Plug Configuration Control (0x0ABC) on page 17- 0x0AC8 DWord SMBUSSTS SMBUSSTS - SMBus Status (0x0AC8) on page 17-23 0x0ACC DWord SMBUSCTL SMBUSCTL - SMBus Control (0x0ACC) on page 17-25 0x0AD0 DWord EEPROMINTF...
Page 214 IDT Register Organization Notes PES48H12AG2 User Manual 15 - 18 April 5, 2013...
Page 215: Pci To Pci Bridge And Proprietary Port Specific Registers
Chapter 16 PCI to PCI Bridge and Proprie- tary Port Specific Registers ® Type 1 Configuration Header Registers VID - Vendor Identification Register (0x000) Field Default Type Description Field Name Value 15:0 0x111D Vendor Identification. This field contains the 16-bit vendor ID value assigned to IDT.
Page 216 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value VGAS VGA Palette Snoop. Not applicable. PERRE Parity Error Response Enable. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit (MDPED) in the PCI Status (PCISTS) register.
Page 217 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value MDPED RW1C Master Data Parity Error Detected. This bit is set by the bridge function if the PERRE bit in the PCI Command register (PCICMD) is set to 0x1 and either of the following two conditions occurs: the function receives a Poisoned Completion going Downstream, or the function transmits a Poisoned Request Upstream.
Page 218 IDT PCI to PCI Bridge and Proprietary Port Specific Registers CLS - Cache Line Size Register (0x00C) Field Default Type Description Field Name Value 0x00 Cache Line Size. This field has no effect on the bridge’s function- ality but may be read and written by software. This field is implemented for compatibility with legacy software.
Page 219 IDT PCI to PCI Bridge and Proprietary Port Specific Registers PBUSN - Primary Bus Number Register (0x018) Field Default Type Description Field Name Value PBUSN Primary Bus Number. This field is used to record the bus number of the PCI bus segment to which the primary interface of the bridge is connected.
Page 220 IDT PCI to PCI Bridge and Proprietary Port Specific Registers IOLIMIT - I/O Limit Register (0x01D) Field Default Type Description Field Name Value IOCAP I/O Capability. Indicates if the bridge supports 16-bit or 32-bit I/O addressing. This bit always reflects the value of the IOCAP field in the IOBASE register.
Page 221 IDT PCI to PCI Bridge and Proprietary Port Specific Registers MBASE - Memory Base Register (0x020) Field Default Type Description Field Name Value Reserved Reserved field. 15:4 MBASE 0xFFF Memory Address Base. The MBASE and MLIMIT registers are used to control the forwarding of non-prefetchable transactions between the primary and secondary interfaces of the bridge.
Page 222 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value Reserved Reserved field. 15:4 PMLIMIT Prefetchable Memory Address Limit. The PMBASE, PMBASEU, PMLIMIT and PMLIMITU registers are used to control the forward- ing of prefetchable transactions between the primary and second- ary interfaces of the bridge.
Page 223 IDT PCI to PCI Bridge and Proprietary Port Specific Registers CAPPTR - Capabilities Pointer Register (0x034) Field Default Type Description Field Name Value CAPPTR 0x40 Capabilities Pointer. This field specifies a pointer to the head of the capabilities structure. EROMBASE - Expansion ROM Base Address Register (0x038) Field Default Type...
Page 224 IDT PCI to PCI Bridge and Proprietary Port Specific Registers BCTL - Bridge Control Register (0x03E) Field Default Type Description Field Name Value PERRE Parity Error Response Enable. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit (MDPED) in the Secondary Status (SECSTS) register.
Page 225: Pci Express Capability Structure
IDT PCI to PCI Bridge and Proprietary Port Specific Registers PCI Express Capability Structure PCIECAP - PCI Express Capability (0x040) Field Default Type Description Field Name Value CAPID 0x10 Capability ID. The value of 0x10 identifies this capability as a PCI Express capability structure.
Page 226 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value E0AL Endpoint L0s Acceptable Latency. This field indicates the acceptable total latency that an endpoint can withstand due to tran- sition from the L0s state to the L0 state. The value is hardwired to 0x0 as this field is only applicable to end- point functions.
Page 227 IDT PCI to PCI Bridge and Proprietary Port Specific Registers PCIEDCTL - PCI Express Device Control (0x048) Field Default Type Description Field Name Value CEREN Correctable Error Reporting Enable. This bit controls reporting of correctable errors. NFEREN Non-Fatal Error Reporting Enable. This bit controls reporting of non-fatal errors.
Page 228 IDT PCI to PCI Bridge and Proprietary Port Specific Registers PCIEDSTS - PCI Express Device Status (0x04A) Field Default Type Description Field Name Value RW1C Correctable Error Detected. This bit indicates the status of cor- rectable errors. Errors are logged in this register regardless of whether error reporting is enabled or not.
Page 229 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value MAXLNK- HWINIT Maximum Link Width. This field indicates the maximum link width WDTH of the given PCI Express link. This field may be overridden to allow the link width to be forced to a smaller value.
Page 230 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value Upstream: Link Bandwidth Notification Capability. When set, this bit indi- cates support for the link bandwidth notification status and interrupt mechanisms. The switch downstream ports support the capability. Downstream: This field is not applicable for the upstream port and must be zero.
Page 231 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value CCLK Common Clock Configuration. When set, this bit indicates that this port and the port at the opposite end of the link are operating with a distributed common reference clock.
Page 232 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value HWINIT Negotiated Link Width. This field indicates the negotiated width of the link. 00 0001b - x1 00 0010b - x2 00 0100b - x4 00 1000b - x8 00 1100b - x12 01 0000b - x16...
Page 233 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value LABWSTS RW1C Link Autonomous Bandwidth Status. This bit is set to indicate that either that the PHY has autonomously changed link speed or width for reasons other than to attempt to correct unreliable link operation.
Page 234 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value 14:7 SPLV Slot Power Limit Value. In combination with the Slot Power Limit Scale, this field specifies the upper limit on power supplied by the slot.
Page 235 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value PFDE HWINIT Power Fault Detected Enable. This bit when set enables the gen- eration of a Hot-Plug interrupt or wake-up event on a power fault event.
Page 236 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value HWINIT Power Indicator Control. When read, this register returns the cur- rent state of the Power Indicator. Writing to this register sets the indicator.
Page 237 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value MRLSC RW1C MRL Sensor Changed. Set when an MRL Sensor state change is detected. RW1C Presence Detected Changed. Set when a Presence Detected change is detected.
Page 238 IDT PCI to PCI Bridge and Proprietary Port Specific Registers PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064) Field Default Type Description Field Name Value Reserved Reserved field. ARIFS ARI Forwarding Supported. This bit is set to indicate that the switch supports ARI Forwarding.
Page 239 IDT PCI to PCI Bridge and Proprietary Port Specific Registers PCIELCTL2 - PCI Express Link Control 2 (0x070) Field Default Type Description Field Name Value Target Link Speed. For downstream ports, this field sets an upper Sticky limit on the link operational speed by restricting the values adver- tised by the upstream component in its training sequences.
Page 240 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value Transmit Margin. This field controls the value of the non de- Sticky emphasized voltage level at the transmitter pins. This field is reset to 0x0 on entry to the LTSSM Polling.Configuration substate.
Page 241: Power Management Capability Structure
IDT PCI to PCI Bridge and Proprietary Port Specific Registers PCIELSTS2 - PCI Express Link Status 2 (0x072) Field Default Type Description Field Name Value Current De-emphasis. The value of this bit indicates the current de-emphasis level when the link operates in 5.0 Gbps. 0x0 - De-emphasis level = -6.0 dB 0x1 - De-emphasis level = -3.5 dB The value of this bit in undefined when the link operates at...
Page 242 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value 18:16 Power Management Capability Version. This field indicates compliance with version two of the specification. Complies with version the PCI Bus Power Management Interface Specification, Revision 1.2.
Page 243: Message Signaled Interrupt Capability Structure
IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value PMEE PME Enable. When this bit is set, PME message generation is Sticky enabled for the port. If a hot plug wake-up event is desired when exiting the D3 cold state, then this bit should be set during serial EEPROM initializa- tion.
Page 244 IDT PCI to PCI Bridge and Proprietary Port Specific Registers MSIADDR - Message Signaled Interrupt Address (0x0D4) Field Default Type Description Field Name Value Reserved Reserved field. 31:2 ADDR Message Address. This field specifies the lower portion of the DWORD address of the MSI memory write transaction. The switch assumes that all downstream port generated MSIs are targeted to the root and routes these transactions to the upstream port.
Page 245: Subsystem Id And Subsystem Vendor Id
IDT PCI to PCI Bridge and Proprietary Port Specific Registers Subsystem ID and Subsystem Vendor ID SSIDSSVIDCAP - Subsystem ID and Subsystem Vendor ID Capability (0x0F0) Field Default Type Description Field Name Value CAPID Capability ID. The value of 0xD identifies this capability as a SSID/ SSVID capability structure.
Page 246: Advanced Error Reporting (Aer) Enhanced Capability
IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value 11:8 EREG Extended Register Number. This field selects the extended con- figuration register number as defined by Section 7.2.2 of the PCI Express Base Specification, Rev. 2.0. The value of this register must not be programmed to point to the address offset of this register (i.e., 0xF8) or the ECFGDATA regis- ter (i.e., 0xFC).
Page 247 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value Reserved Reserved field. DLPERR RW1C Data Link Protocol Error Status. This bit is set when a data link Sticky layer protocol error is detected. SDOENERR RW1C Surprise Down Error Status.
Page 248 IDT PCI to PCI Bridge and Proprietary Port Specific Registers AERUEM - AER Uncorrectable Error Mask (0x108) Field Default Type Description Field Name Value UDEF Undefined. This bit is no longer used in this version of the specifi- Sticky cation. Reserved Reserved field.
Page 249 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value UECOMP Unexpected Completion Mask. When this bit is set, the corre- Sticky sponding bit in the AERUES register is masked. When a bit is masked in the AERUES register, the corresponding event is not logged in the advanced capability structure, the First Error Pointer field (FEPTR) in the AERCTL register is not updated, and an error...
Page 250 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value Uncorrectable Internal Error Mask. When this bit is set, the cor- Sticky responding bit in the AERUES register is masked. When a bit is masked in the AERUES register, the corresponding event is not logged in the advanced capability structure, the First Error Pointer field (FEPTR) in the AERCTL register is not updated, and an error...
Page 251 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value COMPTO Completion Timeout Severity. A switch port does not initiate non- posted requests on its own behalf. Therefore, this field is hardwired to zero. CABORT Completer Abort Severity.
Page 252 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value BADTLP RW1C Bad TLP Status. This bit is set when a bad TLP is detected. Sticky BADDLLP RW1C Bad DLLP Status. This bit is set when a bad DLLP is detected. Sticky RPLYROVR RW1C...
Page 253 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value BADDLLP Bad DLLP Mask. When this bit is set, the corresponding bit in the Sticky AERCES register is masked. When a bit is masked in the AERCES register, the corresponding event is not reported to the root com- plex.
Page 254 IDT PCI to PCI Bridge and Proprietary Port Specific Registers AERCTL - AER Control (0x118) Field Default Type Description Field Name Value FEPTR First Error Pointer. This field contains a pointer to the bit in the Sticky AERUES register that resulted in the first reported error. This field is valid only when the bit in the AERUES register pointed to by this field is set.
Page 255: Device Serial Number Enhanced Capability
IDT PCI to PCI Bridge and Proprietary Port Specific Registers AERHL4DW - AER Header Log 4th Doubleword (0x128) Field Default Type Description Field Name Value 31:0 Header Log. This field contains the 4th doubleword of the TLP Sticky header that resulted in the first reported uncorrectable error. Device Serial Number Enhanced Capability SNUMCAP - Serial Number Capabilities (0x180) Field...
Page 256: Pci Express Virtual Channel Capability
IDT PCI to PCI Bridge and Proprietary Port Specific Registers PCI Express Virtual Channel Capability PCIEVCECAP - PCI Express VC Enhanced Capability Header (0x200) Field Default Type Description Field Name Value 15:0 CAPID Capability ID. The value of 0x2 indicates a virtual channel capabil- ity structure.
Page 257 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value 31:24 VCATBLOFF VC Arbitration Table Offset. Not applicable (only the default VC 0 is implemented). PVCCTL - Port VC Control (0x20C) Field Default Type Description Field...
Page 258 IDT PCI to PCI Bridge and Proprietary Port Specific Registers VCR0CTL- VC Resource 0 Control (0x214) Field Default Type Description Field Name Value TCVCMAP bit 0: 0xFF TC/VC Map. This field indicates the TCs that are mapped to the VC resource. Each bit corresponds to a TC.
Page 259 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value VCNEG VC Negotiation Pending. This bit is not applicable for VC0 and is therefore hardwired to 0x0. 31:18 Reserved Reserved field. VCR0TBL0 - VC Resource 0 Port Arbitration Table Entry 0 (0x240) Field Default Type...
Page 260 IDT PCI to PCI Bridge and Proprietary Port Specific Registers VCR0TBL1 - VC Resource 0 Port Arbitration Table Entry 1 (0x244) Field Default Type Description Field Name Value PHASE8 Phase 8. This field contains the port ID for the corresponding port arbitration period.
Page 261: Power Budgeting Enhanced Capability
IDT PCI to PCI Bridge and Proprietary Port Specific Registers VCR0TBL3 - VC Resource 0 Port Arbitration Table Entry 3 (0x24C) Field Default Type Description Field Name Value PHASE24 Phase 24. This field contains the port ID for the corresponding port arbitration period.
Page 262 IDT PCI to PCI Bridge and Proprietary Port Specific Registers PWRBDSEL - Power Budgeting Data Select (0x284) Field Default Type Description Field Name Value DVSEL Data Value Select. This field selects the Power Budgeting Data Value (PWRBDVx) register whose contents are reported in the Data (DATA) field of the Power Budgeting Data (PWRBD) register.
Page 263: Acs Extended Capability
IDT PCI to PCI Bridge and Proprietary Port Specific Registers ACS Extended Capability ACSECAPH - ACS Extended Capability Header (0x320) Field Default Type Description Field Name Value 15:0 CAPID Capability ID. The value of 0xD indicates an ACS extended capa- bility structure.
Page 264 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value Upstre Upstream ACS Upstream Forwarding. If set, indicates the port implements Port: ACS Upstream Forwarding. Port: Downstream Down- Port: stream Port: Upstre Upstream ACS P2P Egress Control.
Page 265 IDT PCI to PCI Bridge and Proprietary Port Specific Registers ACSCTL - ACS Control Register (0x326) Field Default Type Description Field Name Value Upstream Port: ACS Source Validation Enable. When set, the port performs ACS Source Validation. Downstream NOTE: This field remains read-write (RW) for downstream ports, Port: even if the corresponding bit in the ACSCAP register is cleared.
Page 266: Multicast Extended Capability
IDT PCI to PCI Bridge and Proprietary Port Specific Registers ACSECV - ACS Egress Control Vector (0x328) Field Default Type Description Field Name Value 15:0 See Description Egress Control Vector. This field is used to configure ACS peer- to-peer egress control. The value in this field is only valid when ACS peer-to-peer egress control is enabled in the ACSCTL regis- ter.
Page 267 IDT PCI to PCI Bridge and Proprietary Port Specific Registers MCCAP - Multicast Capability (0x334) Field Default Type Description Field Name Value MAXGROUP 0x1F Max Multicast Groups. This field indicates the default number of multicast groups supported by the switch partition, which is 32. The maximum number of supported groups is 64, and this field may be re-programmed during initial switch configuration (e.g., via EEPROM) to 0x3F to enable support for 64 multicast groups.
Page 268 IDT PCI to PCI Bridge and Proprietary Port Specific Registers MCBARH- Multicast Base Address High (0x33C) Field Default Type Description Field Name Value 31:0 MCBARH Multicast BAR High. This field specifies the upper 32-bits (i.e., bits 32 through 63) of the multicast BAR. The behavior is undefined if bits in this field corresponding to address bits that contain the multicast group number or those less than the multicast index position (i.e., INDEXPOS) are non-zero.
Page 269 IDT PCI to PCI Bridge and Proprietary Port Specific Registers MCBLKALLL- Multicast Block All Low (0x348) Field Default Type Description Field Name Value 31:0 MCBLKALL Multicast Block All. Each bit in this field corresponds to one of the lower 32 multicast groups (e.g., bit 0 corresponds to multicast group 0, bit 1 corresponds to multicast group 1, and so on).
Page 270 IDT PCI to PCI Bridge and Proprietary Port Specific Registers MCBLKUTH - Multicast Block Untranslated High (0x354) Field Default Type Description Field Name Value 31:0 MCBLKUT Multicast Block Untranslated. Each bit in this field corresponds to one of the upper 32 multicast groups (e.g., bit 0 corresponds to multicast group 32, bit 1 corresponds to multicast group 33, and so on).
Page 271: Proprietary Port Specific Registers
IDT PCI to PCI Bridge and Proprietary Port Specific Registers Proprietary Port Specific Registers Port Control and Status Registers PCIESCTLIV - PCI Express Slot Control Initial Value (0x420) Field Default Type Description Field Name Value ABPE Attention Button Pressed Enable. SWSticky This field contains the initial value of the corresponding field in the PCI Express Slot Control (PCIESCTL) register when the corre-...
Page 272 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value CCIE Command Complete Interrupt Enable. SWSticky This field contains the initial value of the corresponding field in the PCI Express Slot Control (PCIESCTL) register when the corre- sponding slot or hot-plug capability is enabled.
Page 273: Internal Error Control And Status Registers
IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value Reserved Reserved field. DLLLASCE Data Link Layer Link Active State Change Enable. SWSticky This field contains the initial value of the corresponding field in the PCI Express Slot Control (PCIESCTL) register when the corre- sponding slot or hot-plug capability is enabled.
Page 274 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value IFBDATDBE RW1C IFB Data Double Bit Error. This bit is set when a double bit ECC SWSticky error is detected in the IFB data RAM. IFBCTLSBE RW1C IFB Control Single Bit Error.
Page 275 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value EFBPTLPTO EFB Posted TLP Time-Out. When this bit is set, the correspond- SWSticky ing error bit in the IERRORSTS register is masked from reporting an internal error to the AER Capability Structure.
Page 276 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value EFBCTLDBE EFB Control Double Bit Error. When this bit is set, the corre- SWSticky sponding error bit in the IERRORSTS register is masked from reporting an internal error to the AER Capability Structure.
Page 277 IDT PCI to PCI Bridge and Proprietary Port Specific Registers IERRORSEV - Internal Error Reporting Severity (0x48C) Field Default Type Description Field Name Value IFBPTLPTO IFB Posted TLP Time-Out. This bit controls how an unmasked SWSticky error of the corresponding type is reported. When this bit is set and the corresponding status bit is set and unmasked, then the error is reported as an uncorrectable internal error.
Page 278 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value IFBDATDBE IFB Data Double Bit Error. This bit controls how an unmasked SWSticky error of the corresponding type is reported. When this bit is set and the corresponding status bit is set and unmasked, then the error is reported as an uncorrectable internal error.
Page 279 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value Unreliable Link Detected. This bit controls how an unmasked SWSticky error of the corresponding type is reported. When this bit is set and the corresponding status bit is set and unmasked, then the error is reported as an uncorrectable internal error.
Page 280 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value IFBDATDBE IFB Data Double Bit Error. Writing a one to this bit sets the corre- sponding bit in the IERRORSTS register. This bit always returns a value of zero when read.
Page 281: Physical Layer Control And Status Registers
IDT PCI to PCI Bridge and Proprietary Port Specific Registers Physical Layer Control and Status Registers SERDESCFG - SerDes Configuration (0x510) Field Default Type Description Field Name Value RCVD_OVRD Receiver Detect Override. Each bit in this register corresponds to SWSticky a SerDes lane.
Page 282 IDT PCI to PCI Bridge and Proprietary Port Specific Registers LANESTS1 - Lane Status 1 (0x520) Field Default Type Description Field Name Value RW1C Receiver Underflow Detected. Each bit in this field corresponds Sticky to a SerDes lane associated with the port. A bit is set when the corresponding link receiver is unable to com- pensate for clock variance between link partners and has inserted one or more zero bytes into the stream.
Page 283 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value 13:12 Reserved Reserved field. ILSCC Downstream: Initial Link Speed Change Control. This field determines whether a port automatically initiates a speed change to Gen2 speed, if Gen2 speed is permissible, after initial entry to L0 from Detect.
Page 284: Power Management Control And Status Registers
IDT PCI to PCI Bridge and Proprietary Port Specific Registers Power Management Control and Status Registers L1ASPMRTC - L1 ASPM Rejection Timer Control (0x710) Field Default Type Description Field Name Value 13:0 MTL1ER 0x947 Minimum Time between L1 Entry Requests. This field indicates SWSticky the minimum time (in 250Mhz cycles) that the port waits between detecting consecutive L1 ASPM entry requests.
Page 285 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value Reserved Reserved field. 15:6 CNSTLIMIT 0x10 Constant Limit. This field is used to control the algorithm used to SWSticky compute the completion size estimate for non-posted read requests when request metering is enabled.
Page 286: Global Address Space Access Registers
IDT PCI to PCI Bridge and Proprietary Port Specific Registers Global Address Space Access Registers GASAADDR - Global Address Space Access Address (0xFF8) Field Default Type Description Field Name Value Reserved Reserved field. 18:2 GADDR Global Address. This field selects the system address of the reg- ister to be accessed via the GASADATA register.
Page 287 IDT PCI to PCI Bridge and Proprietary Port Specific Registers PES48H12AG2 User Manual 16 - 73 April 5, 2013...
Page 288 IDT PCI to PCI Bridge and Proprietary Port Specific Registers PES48H12AG2 User Manual 16 - 74 April 5, 2013...
Page 289: Switch Configuration And Status Registers
Chapter 17 Switch Configuration and Status Registers ® Switch Control and Status Registers SWCTL - Switch Control (0x0000) Field Default Type Description Field Name Value Reserved Reserved field. RSTHALT HWINIT Reset Halt. When this bit is set, all of the switch logic except the SWSticky SMBus interface remains in a quasi-reset state.
Page 290 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value 10:9 DDDNC Disable Downstream Device Number Checking. This field con- SWSticky trols the extent to which device numbers are checked by down- stream ports. This field is present for backwards compatibility with earlier IDT switches that implement a proprietary version of ARI forwarding.
Page 291 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value RSTHALT HWINIT Reset Halt. Boot configuration vector value sampled during a switch fundamental reset. 20:17 Reserved Reserved field. 23:21 CLKMODE Clock Mode. Boot configuration vector value sampled during a switch fundamental reset.
Page 292: Internal Switch Timer
IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value 13:12 P6CLKMODE HWINIT Port 6 Clocking Mode. See P0CLKMODE description. Sticky 15:14 P7CLKMODE HWINIT Port 7 Clocking Mode. See P0CLKMODE description. Sticky 17:16 P8CLKMODE HWINIT Port 8 Clocking Mode. See P0CLKMODE description. Sticky 19:18 P9CLKMODE...
Page 293: Switch Partition And Port Registers
IDT Switch Configuration and Status Registers Switch Partition and Port Registers SWPART[11:0]CTL - Switch Partition x Control Field Default Type Description Field Name Value STATE HWINIT Switch Partition State. This field controls the state of the switch SWSticky partition. 0x0 - (disable) Disabled 0x1 - (active) Active 0x2 - Reserved 0x3 - (reset) Reset...
Page 294 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value USID HWINIT Upstream Port ID. When the Upstream Port (US) bit is set in this register, this field specifies the switch port ID of the port that will act as the upstream port of the switch partition.
Page 295 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value Reserved HWINIT This field is unused in the switch and serves as a place holder for SWSticky the future. 21:20 Reserved HWINIT This field is unused in the switch and serves as a place holder for SWSticky the future.
Page 296: Protection
IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value 13:10 SWPART HWINIT Switch Partition. For operational port modes (i.e., downstream switch port, upstream switch port, NT endpoint, upstream switch port with NT endpoint), this field contains the current switch parti- tion to which the port is attached.
Page 297 IDT Switch Configuration and Status Registers S[11:0]CTL - SerDes x Control Field Default Type Description Field Name Value LANESEL 0x10 Lane Select. This field selects the lane on which the SerDes lane SWSticky control registers (S[x]TXLCTL0, S[x]TXLCTL1, S[x]RXLCTL, and S[x]RXEQLCTL) operate when written. 0x0 - Operate on lane 0 only 0x1 - Operate on lane 1 only 0x2 - Operate on lane 2 only...
Page 298 IDT Switch Configuration and Status Registers S[11:0]TXLCTL0 - SerDes x Transmitter Lane Control 0 Field Default Type Description Field Name Value CDC_FS3DBG1 Transmit Driver Coarse De-Emphasis Control for Full Swing SWSticky mode in Gen1. This field provides coarse level control of the trans- mit driver de-emphasis level in full-swing mode and Gen 1 data rate (i.e., 2.5 GT/s).
Page 299 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value 11:10 TX_EQ_3DBG2 Transmit Equalization for Full Swing Mode with -3.5dB in SWSticky Gen2. This field controls the transmit equalization in Gen 2 data rate, when the SDE field in the associated port’s PCIELCTL2 regis- ter is set to -3.5 dB de-emphasis.
Page 300 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value 25:23 TX_FSLEW_G2 Transmit Driver Fine Slew Adjustment in Gen2. This field allows SWSticky fine adjustment of the output driver’s slew rate at Gen 2 data-rate, for the lane(s) selected by the Lane Select (LANESEL[3:0]) field in the SerDes Control (S[x]CTL) register.
Page 301 IDT Switch Configuration and Status Registers S[11:0]TXLCTL1 - SerDes x Transmitter Lane Control 1 Field Default Type Description Field Name Value TDVL_FS3DBG1 0x11 Transmit Driver Voltage Level for Full-Swing Mode with -3.5dB SWSticky De-emphasis in Gen1. This field controls the SerDes transmit driver voltage level in full- swing mode and Gen 1 data rate (i.e., 2.5 GT/s).
Page 302 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value 15:13 FDC_FS3DBG2 Transmit Driver Fine De-emphasis Control for Full Swing SWSticky Mode with -3.5dB in Gen 2. This field provides fine level control of the transmit driver de- emphasis level in Gen 2 mode, when the SDE field in the associ- ated port’s PCIELCTL2 register is set to -3.5dB de-emphasis.
Page 303 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value 23:21 FDC_FS6DBG2 Transmit Driver Fine De-emphasis Control for Full Swing SWSticky Mode with -6.0dB in Gen 2. This field provides fine level control of the transmit driver de- emphasis level in Gen 2 mode, when the SDE field in the associ- ated port’s PCIELCTL2 register is set to -6.0dB de-emphasis.
Page 304: General Purpose I/O Registers
IDT Switch Configuration and Status Registers S[11:0]RXEQLCTL - SerDes x Receiver Equalization Lane Control Field Default Type Description Field Name Value RXEQZ Receiver Equalization Zero. Amplifies the high-frequency gain of SWSticky the equalizer. A value of 0x0 results in the smallest amount of high frequency gain.
Page 305 IDT Switch Configuration and Status Registers GPIOFUNC1 - General Purpose I/O Function 1 (0x0A94) Field Default Type Description Field Name Value 21:0 GPIOFUNC GPIO Function. Each bit in this field controls the corresponding SWSticky GPIO pin. When set, the corresponding GPIO pin operates as the selected alternate function.
Page 306 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value 25:24 AFSEL12 GPIO Pin 12 Alternate Function Select. See AFSEL0 field SWSticky description in the GPIOAFSEL0 register. 27:26 AFSEL13 GPIO Pin 13 Alternate Function Select. See AFSEL0 field SWSticky description in the GPIOAFSEL0 register.
Page 307 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value 29:28 AFSEL30 GPIO Pin 30 Alternate Function Select. See AFSEL0 field SWSticky description in the GPIOAFSEL0 register. 31:30 AFSEL31 GPIO Pin 31 Alternate Function Select. See AFSEL0 field SWSticky description in the GPIOAFSEL0 register.
Page 308 IDT Switch Configuration and Status Registers GPIOAFSEL3 - General Purpose I/O Alternate Function Select 3 (0xAA4) Field Default Type Description Field Name Value AFSEL48 GPIO Pin 48 Alternate Function Select. See AFSEL0 field SWSticky description in the GPIOAFSEL0 register. AFSEL49 GPIO Pin 49 Alternate Function Select.
Page 309: Hot-Plug And Smbus Interface Registers
IDT Switch Configuration and Status Registers GPIOD0 - General Purpose I/O Data 0 (0x0AB0) Field Default Type Description Field Name Value 31:0 GPIOD HWINIT GPIO Data. Each bit in this field controls the corresponding GPIO SWSticky pin. Reading this field returns the current value of each GPIO pin regardless of GPIO pin mode (i.e., alternate function or GPIO pin).
Page 310 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value 14:10 HP2GPIOPRT 0x1F Hot-Plug GPIO 2 Port Map. This field selects the switch port SWSticky whose hot-plug signals are mapped to GPIO alternate function HP2 signals. A value of all ones (i.e., 0x1F) indicates that no port is mapped to HPx GPIO alternate function signals.
Page 311 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value 10:9 PDETECT Presence Detect Control. This field controls the manner in which SWSticky presence of an adapter in a slot is reported to the hot-plug control- ler associated with a downstream switch port. 0x0 - (both) Presence of an adapter in the slot is reported as the logical “OR”...
Page 312 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value SSMBADDR HWINIT Slave SMBus Address. This field contains the SMBus address assigned to the slave SMBus interface. Reserved Reserved field. 15:9 MSMBADDR HWINIT Master SMBus Address. This field contains the SMBus address assigned to the master SMBus interface.
Page 313 IDT Switch Configuration and Status Registers SMBUSCTL - SMBus Control (0x0ACC) Field Default Type Description Field Name Value 15:0 MSMBCP HWINIT Master SMBus Clock Prescalar. This field contains a clock pres- SWSticky calar value used during master SMBus transactions. The prescalar clock period is equal to 32 ns multiplied by the value in this field.
Page 314 IDT Switch Configuration and Status Registers EEPROMINTF - Serial EEPROM Interface (0x0AD0) Field Default Type Description Field Name Value 15:0 ADDR EEPROM Address. This field contains the byte address in the Serial EEPROM to be read or written. 23:16 DATA EEPROM Data.
Page 315 IDT Switch Configuration and Status Registers IOEXPADDR1 - SMBus I/O Expander Address 1 (0x0ADC) Field Default Type Description Field Name Value Reserved Reserved field. IOE4ADDR I/O Expander 4 Address. This field contains the SMBus address SWSticky assigned to I/O expander 4 on the master SMBus interface. Reserved Reserved field.
Page 316 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value Reserved Reserved field. 15:9 IOE13ADDR I/O Expander 13 Address. This field contains the SMBus address SWSticky assigned to I/O expander 13 on the master SMBus interface. 31:16 Reserved Reserved field.
Page 317: Jtag Boundary Scan
Chapter 18 JTAG Boundary Scan ® Introduction Notes The JTAG Boundary Scan interface provides a way to test the interconnections between integrated circuit pins after they have been assembled onto a circuit board. There are two pin types present in the switch: AC-coupled and DC-coupled (also called AC and DC pins).
Page 318: Table 18.1 Jtag Pin Descriptions
IDT JTAG Boundary Scan Notes Pin Name Type Description JTAG_TRST_N Input JTAG RESET (active low) Asynchronous reset for JTAG TAP controller (internal pull-up) JTAG_TCK Input JTAG Clock Test logic clock. JTAG_TMS and JTAG_TDI are sampled on the rising edge. JTAG_TDO is output on the falling edge. JTAG_TMS Input JTAG Mode Select.
Page 319: Boundary Scan Chain
IDT JTAG Boundary Scan Boundary Scan Chain Notes Function Pin Name Type Boundary Cell PCI Express Interface PE00RN[3:0] PE00RP[3:0] PE00TN[3:0] PE00TP[3:0] PE01RN[3:0] PE01RP[3:0] PE01TN[3:0] PE01TP[3:0] PE02RN[3:0] PE02RP[3:0] PE02TN[3:0] PE02TP[3:0] PE03RN[3:0] PE03RP[3:0] PE03TN[3:0] PE03TP[3:0] PE04RN[3:0] PE04RP[3:0] PE04TN[3:0] PE04TP[3:0] PE05RN[3:0] PE05RP[3:0] PE05TN[3:0] PE05TP[3:0] PE06RN[3:0] PE06RP[3:0]...
Page 320 IDT JTAG Boundary Scan Notes Function Pin Name Type Boundary Cell PCI Express PE09TN[3:0] Interface (Cont.) PE09TP[3:0] PE10RN[3:0] PE10RP[3:0] PE10TN[3:0] PE10TP[3:0] PE11RN[3:0] PE11RP[3:0] PE11TN[3:0] PE11TP[3:0] GCLKN[1:0] — GCLKP[1:0] P[11:0]CLKN P[11:0]CLKP SMBus MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT General Purpose I/O GPIO[53:0] System Pins CLKMODE[2:0]...
Page 321: Test Data Register (Dr)
IDT JTAG Boundary Scan Notes Function Pin Name Type Boundary Cell SerDes Reference REFRES00 — Resistors REFRES01 — REFRES02 — REFRES03 — REFRES04 — REFRES05 — REFRES06 — REFRES07 — REFRES08 — REFRES09 — REFRES10 — REFRES11 — REFRESPLL — Table 18.2 Boundary Scan Chain (Part 3 of 3) I = Input, O = Output O = Observe, C = Control...
Page 322: Figure 18.3 Diagram Of Observe-Only Input Cell
IDT JTAG Boundary Scan Notes Input To core logic To next cell From previous cell shift_dr clock_dr Figure 18.3 Diagram of Observe-only Input Cell The simplified logic configuration of the output cells is shown in Figure 18.4. EXTEST To Next Cell Data from Core To Output Pad Data from Previous Cell...
Page 323: Instruction Register (Ir)
IDT JTAG Boundary Scan Notes shift_dr EXTEST Output enable from core Data from previous cell OEN to pad clock_dr update_dr I/O pin shift_dr Data from core EXTEST To next cell Figure 18.5 Diagram of Bidirectional Cell The bidirectional cells are composed of only two boundary scan cells. They contain one output enable cell and one capture cell, which contains only one register.
Page 324: Extest
IDT JTAG Boundary Scan Notes Instruction Definition Opcode EXTEST Mandatory instruction allowing the testing of board level interconnec- 000000 tions. Data is typically loaded onto the latched parallel outputs of the boundary scan shift register using the SAMPLE/PRELOAD instruction prior to use of the EXTEST instruction. EXTEST will then hold these values on the outputs while being executed.
Page 325: Clamp
IDT JTAG Boundary Scan Notes Therefore, instead of having to shift many times to get a value through the device, the user only needs to shift one time to get the value from JTAG_TDI to JTAG_TDO. When the TAP controller passes through the CAPTURE-DR state, the value in the BYPASS register is updated to be 0.
Page 326: Extest_Pulse
IDT JTAG Boundary Scan Notes If the Run-Test/Idle state is not entered, the output of the AC pins is not distinguishable from the output of the DC EXTEST instruction. EXTEST_PULSE EXTEST_PULSE is an instruction listed in IEEE 1149.6 JTAG specification and is used to test AC pins during boundary scan by shifting data from TDI to TDO within the Shift-DR-TAP controller State.
Page 327 Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products.

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