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IDT Hot-Plug and Hot-Swap
Notes
PES48H12G2 User Manual
PxPEP
PxPWRGDN
PxRSTN
Figure 10.5 Power Good Controlled Reset Output Mode Operation
The operation of this mode is similar to that of the Power Enable Controlled Reset mode except that
when power is enabled, the negation of the corresponding port reset output occurs as a result of and after
assertion of the slot's Power Good (PxPWRGDN) signal is observed. The time between the assertion of the
PxPWRGDN signal and the negation of the PxRSTN signal is controlled by the value in the Slot Power to
Reset Negation (PWR2RST) field in the HPCFGCTL register.
When slot power is disabled by writing a one to the PCC bit, the corresponding downstream port reset
output is asserted and then slot power is disabled. The time between the assertion of the PxRSTN signal
and the negation of the PxPEP signal is controlled by the value in the Reset Negation to Slot Power
(RST2PWR) field in the HPCFGCTL register.
If at any point while a downstream port is not being reset (i.e., PxRSTN is negated) the power good (i.e.,
PxPWRGDN) is negated, then the corresponding port reset output is immediately asserted.
Hot-Plug Events
The hot-plug controller associated with a downstream port slot may generate an interrupt or wakeup
event.
– Interrupts and wakeup events only affect the partition with which the downstream port is associ-
ated.
Hot-plug interrupts are enabled when the Hot Plug Interrupt Enable (HPIE) bit is set in the corre-
sponding port's PCI Express Slot Control (PCIESCTL) register. The following bits, when set in the PCI
Express Slot Status (PCIESSTS) register, generate an interrupt if not masked by the corresponding bit in
the PCI Express Slot Control (PCIESCTL) register or by the HPIE bit: the Attention Button Pressed (ABP),
Power Fault Detected (PFD), MRL Sensor Changed (MRLSC), Presence Detected Changed (PDC),
Command Completed (CC), and Data Link Layer Active State Change (DLLASC).
When an unmasked hot-plug interrupt is generated, the action taken is determined by the MSI Enable
(EN) bit in the MSI Capability (MSICAP) register and the Interrupt Disable (INTXD) bit in the PCI Command
(PCICMD) register. When the downstream port is in a D3
wakeup event using a PM_PME message instead of an interrupt when the following conditions are satis-
fied. The status bit for an enabled hot-plug event listed below transitions from not set to set.
– Attention button pressed
– Power fault detected
– MRL sensor changed
– Presence detect changed
– Command completed event
– Data link layer state change event
The PME Enable (PMEE) bit in the PCI Power Management Control and Status (PMCSR) is set. If is not
required that the Hot Plug Interrupt Enable (HPIE) bit be set in the corresponding port's PCI Express Slot
Control (PCIESCTL) register in order to generate a wakeup event using a PM_PME message. Software
may clear the HPIE bit to disable interrupt generation while keeping wakeup event generation enabled.
T
PWR2RST
state, then the hot-plug controller generates a
hot
10 - 6
T
RST2PWR
April 5, 2013
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