Serdes Transmitter Control Registers - Renesas IDT 89HPES48H12G2 User Manual

IDT SerDes
Notes
PES48H12G2 User Manual
When the Transmit Margin (TM) field in the port's PCIELCTL2 register is set to 'Normal Operating
Range', the transmitter voltage level for each SerDes lane of the port is controlled via the S[x]TXLCTL0 and
S[x]TXLCTL1 registers. Otherwise, the TM field controls the SerDes voltage directly for all SerDes lanes of
the port.
– For instance, port 0 is associated with SerDes quad 0.
register is set to 'Normal Operating Range', then the S[0]TXLCTL0 and S[0]TXLCTL1 registers
control the operating voltage of the port's SerDes. If the TM field is set to another value, the
SerDes voltage is set to the value in the port's PCIELCTL2.TM field.
– Also, if port 4 operates in merged mode, it is associated with SerDes quads 4 and 5. If the TM field
in the port's PCIELCTL2 register is set to 'Normal Operating Range', then the S[4:5]TXLCTL0 and
S[4:5]TXLCTL1 registers control the operating voltage of the port's SerDes. If the TM field is set
to another value, the SerDes voltage of both SerDes quad 4 and SerDes quad 5 is set to the value
in the PCIELCTL2.TM field of port 4.
De-emphasis levels may also be adjusted on a per-lane basis, using the above mentioned transmitter
control registers. Nominally, de-emphasis levels are set to -3.5 dB, -6.0 dB, or 0 dB (in low-swing mode).
The S[x]TXLCTL0 and S[x]TXLCTL1 registers can be used to modify the nominal values by coarse or fine
steps.

SerDes Transmitter Control Registers

As described above, each SerDes quad is associated with two transmitter control registers
(S[x]TXLCTL0 and S[x]TXLCTL1). Together, these registers allow full programmability of the SerDes trans-
mitter voltage levels and de-emphasis. These registers are segmented into fields that allow programma-
bility of the transmit driver levels under the following PHY operating modes:
– Full-Swing Mode, in Gen1 data rate, with -3.5 dB de-emphasis
– Full-Swing Mode, in Gen2 data rate, with -3.5 dB de-emphasis
– Full-Swing Mode, in Gen2 data rate, with -6.0 dB de-emphasis
– Low-Swing Mode, in Gen1 data rate (no de-emphasis)
– Low-Swing Mode, in Gen2 data rate (no de-emphasis)
The S[x]TXLCTL0 and S[x]TXLCTL1 registers have default values that select the appropriate transmit
driver settings for each of the above modes. These default values may be modified to adjust the drive
levels.
When the Physical layer of the port associated with the SerDes transitions dynamically across these
operating modes, the appropriate driver settings are applied to the SerDes automatically. For example,
when the PHY operates in Full-swing mode at Gen1 data rate with -3.5 dB de-emphasis, the SerDes
transmit settings are set to the values specified in the S[x]TXLCTL0 and S[x]TXLCTL1 registers corre-
sponding to that operating mode. As the PHY changes data rate to Gen2, the SerDes transmit settings are
automatically modified to the values specified in the S[x]TXLCTL0 and S[x]TXLCTL1 registers corre-
sponding to the new operating mode (e.g., Full-Swing mode at Gen2 data rate with -3.5 dB de-emphasis).
Table 8.1 shows the register fields that control the SerDes transmit levels for the operation modes listed
above.
1.
SerDes and Port association are subject to the rules outlined in section SerDes Numbering and Port Association
on page 8-1.
8 - 4
1
If the TM field in the port's PCIELCTL2
April 5, 2013