Transmit Margining Using The Pci Express Link Control 2 Register; Table 8.6 Pci Express Transmit Margining Levels Supported By The Pes48H12G2 - Renesas IDT 89HPES48H12G2 User Manual

IDT SerDes
Notes
PES48H12G2 User Manual
Table 8.5 Transmitter Slew Rate Settings (Part 2 of 2)
Transmit Margining using the PCI Express Link Control
2 Register
When the Transmit Margin (TM) field in the port's PCIELCTL2 register is set to a value other than
'Normal Operating Range', the transmitter voltage levels are controlled by hardware based on the setting of
the TM field, and not by the S[x]TXLCTL0 and S[x]TXLCTL1 registers. Per the PCI Express 2.0 specifica-
tion, transmit margining may be done in full-swing mode or in low-swing mode. Table 8.6 shows the transmit
margining settings supported by the switch.

Table 8.6 PCI Express Transmit Margining Levels supported by the PES48H12G2

Note that in compliance mode (i.e., when the associated port's PHY LTSSM is in the Polling.Compliance
state), the SerDes transmit level is controlled by the TM field in the associated port's PCIELCTL2 register,
and the de-emphasis setting is controlled by the LTSSM based on the rules described in Section 4.2.6.2.2
of the PCI Express 2.0 specification.
– When the LTSSM enters the Polling.Compliance state in full-swing mode, the values for full-swing
margining are applied.
– When the LTSSM enters the Polling.Compliance state in low-swing mode, the values for low-
swing margining are applied.
1.
The TX_AMPBOOST field in the S[x]TXLCTL0 register does have an effect during transmit margining.
2 5
4
2
0
1 5
4
2
0
0 5
4
2
0
1
Full Swing Low Swing
Mode Mode
(mV) (mV)
900 500
700 400
500 300
300 200
200 100
8 - 12
337
269
120
60
340
272
123
50
342
273
127
48
April 5, 2013