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Renesas IDT 89HPES12NT12G2 User Manual

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®

®

IDT

89HPES12NT12G2

®

PCI Express

Switch

User Manual

July 2013

6024 Silver Creek Valley Road, San Jose, California 95138

Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775

Printed in U.S.A.

©2013 Integrated Device Technology, Inc.

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Page 1 ® ® 89HPES12NT12G2 ® PCI Express Switch User Manual July 2013 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2013 Integrated Device Technology, Inc.
Page 2 GENERAL DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use.
Page 3: About This Manual
About This Manual ® Overview Notes This user manual includes hardware and software information on the 89HPES12NT12G2, a member of IDT’s PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O interconnect standard. Finding Additional Information Information not included in this manual such as mechanicals, package pin-outs, and electrical character- istics can be found in the data sheet for this device, which is available from the IDT website (www.idt.com) as well as through your local IDT sales representative.
Page 4: Signal Nomenclature
Notes Chapter 16, “Switch Events,” describes mechanisms provided by the PES12NT12G2 to facilitate communication between roots associated with different partitions as well as for communication between these roots and a management agent. Chapter 17, “Multicast,” describes how the multicast capability enables a single TLP to be forwarded to multiple destinations.
Page 5: Numeric Representations
Notes single clock cycle high-to-low transition low-to-high transition Figure 1 Signal Transitions Numeric Representations To represent numerical values, either decimal, binary, or hexadecimal formats will be used. The binary format is as follows: 0bDDD, where “D” represents either 0 or 1; the hexadecimal format is as follows: 0xDD, where “D”...
Page 6: Register Terminology
Notes bit 31 bit 0 Address of Bytes within Words: Big Endian bit 31 bit 0 Address of Bytes within Words: Little Endian Figure 2 Example of Byte Ordering for “Big Endian” or “Little Endian” System Definition Register Terminology Software in the context of this register terminology refers to modifications made by PCI Express root configuration writes, writes to registers made through the slave SMBus interface, or serial EEPROM register initialization.
Page 7: Use Of Hypertext
Notes Type Abbreviation Description Read and Write Software can both read and write bits with this attribute. Read and Write Clear RW1C Software can read and write to registers/bits with this attribute. However, writing a value of zero to a bit with this attribute has no effect.
Page 8 Notes November 4, 2009: In Chapter 2, added new section Support for Spread Spectrum Clocking (SCC) with updated tables and modified Limitations column in Table 2.6, Clock Frequency Limitations. In chapter 5, added three new sections: Partition State Change Latency, Port Operating Mode Change Latency, and Partition Reconfiguration Latency.
Page 9 Notes Descriptor Prefetching, ECRC Errors, and Completion Timeout sections. In Chapter 16, revised text in section Port AER Errors. In Chapter 17, changed reference from NTMTC to NTMCC in NT Multicast TLP Routing section. In Chapter 21, made the following changes: revised description for MAXLNKSPD bit in PCI Express Link Capabilities register (also applies to same bit in same register in Chapters 23 and 24), revised description for bits in PCI Express Slot Control register.
Page 10 Notes June 21, 2011: In Chapter 5, section Reset Mode Change Behavior, changed fourth bullet to read “The port remains in a Reset state for at least 250 µs.” June 24, 2011: In Chapter 25, added bit BDISCARD to the Switch Control register. July 15, 2011: In Chapter 1, revised section Switch Events and removed “and Signals”...
Page 11: Table Of Contents
Table of Contents ® About This Manual Notes Overview ............................1 Content Summary .......................... 1 Signal Nomenclature ........................2 Numeric Representations ......................3 Data Units ............................3 Register Terminology ........................4 Use of Hypertext ..........................5 Reference Documents ........................5 Revision History ..........................
Page 12 IDT Table of Contents Notes Partition Fundamental Reset ....................3-10 Partition Hot Reset ....................... 3-11 Partition Upstream Secondary Bus Reset ................3-12 Partition Downstream Secondary Bus Reset ............... 3-12 Port Mode Change Reset ......................3-13 Switch Core Overview............................4-1 Switch Core Architecture ........................ 4-1 Ingress Buffer .........................
Page 13 IDT Table of Contents Link Operation Notes Overview............................7-1 Port Merging ........................... 7-1 Port Maximum Link Width....................... 7-1 Polarity Inversion ..........................7-2 Lane Reversal..........................7-2 Link Width Negotiation........................7-4 Link Width Negotiation in the Presence of Bad Lanes ............7-5 Dynamic Link Width Reconfiguration....................
Page 14 IDT Table of Contents Transparent Switch Operation Notes Overview............................10-1 Transaction Routing........................10-1 Virtual Channel Support........................ 10-2 Maximum Payload Size ........................ 10-2 Upstream Port Device Number..................... 10-2 Bus Locking ..........................10-2 Interrupts............................10-4 Downstream Port Interrupts....................10-4 Upstream Port Interrupts ...................... 10-4 Legacy Interrupt Aggregation ....................
Page 15 IDT Table of Contents Non-Transparent Switch Operation Notes Overview............................14-1 Base Address Registers (BARs)....................14-1 BAR Limit..........................14-2 Mapping NT Configuration Space to BAR 0 ................. 14-4 TLP Translation ..........................14-4 Direct Address Translation ....................14-4 Lookup Table Address Translation..................14-5 ID Translation ..........................
Page 16 IDT Table of Contents Notes DMA Multicast ........................15-23 Interrupts............................. 15-24 Virtual Channel (VC) Support ..................... 15-25 Access Control Services (ACS) Support ..................15-25 Power Management........................15-27 Bus Locking ..........................15-27 ECRC Support ..........................15-27 Error Handling..........................15-27 PCI Express Error Handling by the DMA Function............. 15-28 DMA Limitations and Usage Restrictions ...................
Page 17 IDT Table of Contents PCI-to-PCI Bridge Registers Notes Type 1 Configuration Header Registers ..................20-1 PCI Express Capability Structure ....................20-13 PCI Power Management Capability Structure ................20-35 Message Signaled Interrupt Capability Structure ............... 20-37 Subsystem ID and Subsystem Vendor ID .................. 20-38 Extended Configuration Space Access Registers ..............
Page 18 IDT Table of Contents DMA Function Registers Notes Type 0 Configuration Header Registers ..................23-1 PCI Express Capability Structure ....................23-9 PCI Power Management Capability Structure ................23-21 Message Signaled Interrupt Capability Structure ............... 23-23 Extended Configuration Space Access Registers ..............23-24 Advanced Error Reporting (AER) Extended Capability...............
Page 19 IDT Table of Contents Notes Switch Partitioning via serial EEPROM ................26-4 Switch Partitioning via PCI Express Configuration Requests..........26-5 Dynamic Port and Partition Reconfiguration................. 26-8 I/O Load Balancing: Downstream Port Migration ..............26-8 Non-Transparent Bridge (NTB) Usage Models................26-11 PES12NT12G2 as a Multiprocessor System Interconnect..........
Page 20 IDT Table of Contents Notes PES12NT12G2 User Manual July 10, 2013...
Page 21 List of Tables ® Table 1.1 PES12NT12G2 Device IDs....................1-1 Notes Table 1.2 PES12NT12G2 Revision ID....................1-1 Table 1.3 Operating Modes Supported by Each Port ................1-6 Table 2.1 Ports That Must Operate with the Same Port Clocking Mode ..........2-2 Table 2.2 PxCLK Usage When a Port Operates in Local Port Clocked Mode ........
Page 22 IDT List of Tables Notes Table 10.10 Conditions Handled as Unsupported Requests (UR) by the PCI-to-PCI Bridge Function........................... 10-15 Table 10.11 Conditions Handled as Unexpected Completions (UC) by the PCI-to-PCI Bridge Function........................... 10-16 Table 10.12 Ingress TLP Formation Checks associated with the PCI-to-PCI Bridge Function... 10-17 Table 10.13 Egress Malformed TLP Error Checks................
Page 23 IDT List of Tables Notes Table 14.7 Error Logging at Each Function for UR Example # 1 ............14-34 Table 14.8 Error Logging at Each Function for UR Example # 2 ............14-35 Table 14.9 Error Logging at Each Function for Poisoned TLP Example ........... 14-36 Table 14.10 Error Logging at Each Function for Poisoned TLP Example ...........
Page 24 IDT List of Tables Notes PES12NT12G2 User Manual July 10, 2013...
Page 25 List of Figures ® Figure 1.1 PES12NT12G2 Block Diagram ..................1-3 Notes Figure 1.2 Logical Representation of a Port with PCI-to-PCI bridge, NT, and DMA Functions ..1-5 Figure 1.3 Transparent PCI Express Switch ..................1-6 Figure 1.4 Partitionable PCI Express Switch ..................1-7 Figure 1.5 Non-Transparent Bridge ....................1-8 Figure 1.6...
Page 26 IDT List of Figures Notes Figure 10.5 ACS Peer-to-Peer Request Re-direct by an Upstream PCI-to-PCI Bridge Function ..10-9 Figure 10.6 Error Checking and Logging on a Received TLP ............10-21 Figure 11.1 Hot-Plug on Switch Downstream Slots Application ............11-1 Figure 11.2 Hot-Plug with Switch on Add-In Card Application ............11-2 Figure 11.3 Hot-Plug with Carrier Card Application ................11-2...
Page 27 IDT List of Figures Notes Figure 15.13 Path Taken by a TLP Emitted by the DMA When it is NT Multicasted ......15-24 Figure 15.14 Example of ACS Peer-to-Peer Request Redirect Applied by the DMA Function ...15-27 Figure 15.15 DMA Function’s Error Checking and Logging on a Received TLP ........15-36 Figure 16.1 Switch Event Detection and Signaling Mechanism ............16-2 Figure 16.2...
Page 28 IDT List of Figures Notes PES12NT12G2 User Manual xviii July 10, 2013...
Page 29 Register List ® ACSCAP - ACS Capability (0x324) ...................... 22-48 Notes ACSCAP - ACS Capability (0x324) ...................... 23-37 ACSCAP - ACS Capability Register (0x324)..................20-55 ACSCTL - ACS Control (0x326)......................22-49 ACSCTL - ACS Control (0x326)......................23-37 ACSCTL - ACS Control Register (0x326)..................... 20-57 ACSECAPH - ACS Extended Capability Header (0x320) ..............
Page 30 IDT Register List Notes BAR2 - Base Address Register 2 (0x018)....................22-7 BAR2 - Base Address Register 2 (0x018)....................23-6 BAR3 - Base Address Register 3 (0x01C) ....................22-8 BAR3 - Base Address Register 3 (0x01C) ....................23-6 BAR4 - Base Address Register 4 (0x020)....................22-9 BAR4 - Base Address Register 4 (0x020)....................23-6 BAR5 - Base Address Register 5 (0x024).....................22-10 BAR5 - Base Address Register 5 (0x024)....................23-7...
Page 31 IDT Register List Notes DMAC[1:0]DPTRL - DMA Channel Descriptor Pointer Low (0x528/628)..........23-56 DMAC[1:0]DSCTL - DMA Channel Destination Stride Control (0x520/620) .........23-55 DMAC[1:0]ERRMSK - DMA Channel Error Mask (0x514/614) .............23-53 DMAC[1:0]ERRSTS - DMA Channel Error Status (0x510/610) ............23-52 DMAC[1:0]MSK - DMA Channel Status Mask (0x50C/60C) ..............23-51 DMAC[1:0]NDPTRH - DMA Channel Next Descriptor Pointer High (0x534/634) .........23-57 DMAC[1:0]NDPTRL - DMA Channel Next Descriptor Pointer Low (0x530/630)........23-57 DMAC[1:0]RRCTL - DMA Channel Request Rate Control (0x524/624) ..........23-55...
Page 32 IDT Register List Notes INDBELLMSK - NT Inbound Doorbell Mask (0x42C)................22-63 INDBELLSTS - NT Inbound Doorbell Status (0x428)................22-62 INMSG[3:0] - Inbound Message [3:0] (0x440-44C)................22-63 INMSGSRC[3:0] - Inbound Message Source [3:0] (0x450-45C)............22-63 INTRLINE - Interrupt Line (0x03C)......................22-12 INTRLINE - Interrupt Line (0x03C)......................23-8 INTRLINE - Interrupt Line Register (0x03C) ..................20-11 INTRPIN - Interrupt PIN (0x03D)......................22-12 INTRPIN - Interrupt PIN (0x03D)......................23-8...
Page 33 IDT Register List Notes MCRCVL- Multicast Receive Low (0x340) ....................20-61 MCRCVL- Multicast Receive Low (0x340) ....................22-52 MINGNT - Minimum Grant (0x03E).......................22-12 MINGNT - Minimum Grant (0x03E)......................23-8 MLIMIT - Memory Limit Register (0x022)....................20-8 MSGSTS - Message Status (0x460) .....................22-64 MSGSTSMSK - Message Status Mask (0x464)..................22-65 MSIADDR - Message Signaled Interrupt Address (0x0D4)..............20-37 MSIADDR - Message Signaled Interrupt Address (0x0D4)..............22-30 MSIADDR - Message Signaled Interrupt Address (0x0D4)..............23-24...
Page 34 IDT Register List Notes PCIEDCAP - PCI Express Device Capabilities (0x044) ................20-14 PCIEDCAP - PCI Express Device Capabilities (0x044) ................22-13 PCIEDCAP - PCI Express Device Capabilities (0x044) ................23-10 PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064) ..............20-30 PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064) ..............22-22 PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064) ..............23-18 PCIEDCTL - PCI Express Device Control (0x048)................20-16 PCIEDCTL - PCI Express Device Control (0x048)................22-15...
Page 35 IDT Register List Notes PMCAP - PCI Power Management Capabilities (0x0C0)..............20-35 PMCAP - PCI Power Management Capabilities (0x0C0)..............22-28 PMCAP - PCI Power Management Capabilities (0x0C0)..............23-21 PMCSR - PCI Power Management Control and Status (0x0C4) ............20-36 PMCSR - PCI Power Management Control and Status (0x0C4) ............22-28 PMCSR - PCI Power Management Control and Status (0x0C4) ............23-22 PMLIMIT - Prefetchable Memory Limit Register (0x026) ................20-9 PMLIMITU - Prefetchable Memory Limit Upper Register (0x02C) ............20-10...
Page 36 IDT Register List Notes SNUMCAP - Serial Number Capabilities (0x180) .................20-50 SNUMCAP - Serial Number Capabilities (0x180) .................22-43 SNUMLDW - Serial Number Lower Doubleword (0x184) ..............20-50 SNUMLDW - Serial Number Lower Doubleword (0x184) ..............22-44 SNUMUDW - Serial Number Upper Doubleword (0x188)..............20-51 SNUMUDW - Serial Number Upper Doubleword (0x188)..............22-44 SSIDSSVID - Subsystem ID and Subsystem Vendor ID (0x0F4) ............20-39 SSIDSSVID - Subsystem ID and Subsystem Vendor ID (0x0F4) ............22-31...
Page 37: Pes12Nt12G2 Device Overview
Chapter 1 PES12NT12G2 Device Overview ® Overview Notes The 89HPES12NT12G2 is a member of the IDT family of PCI Express® switching solutions. The PES12NT12G2 is a 12-lane, 12-port system interconnect switch optimized for PCI Express Gen2 packet switching in high-performance applications, supporting multiple simultaneous peer-to-peer traffic flows. Target applications include multi-host or intelligent I/O based systems where inter-domain communication is required, such as servers, storage, communications, and embedded systems.
Page 38: Jtag Id
IDT PES12NT12G2 Device Overview JTAG ID Notes The JTAG ID is: – Version: Same value as Revision ID. See Table 1.2 – Part number: Same value as base Device ID. See Table 1.1. – Manufacture ID: 0x33 – LSB: 0x1 SSID/SSVID The PES12NT12G2 contains the mechanisms necessary to implement the PCI-to-PCI bridge Subsystem ID and Subsystem Vendor ID capability structure.
Page 39: Port Operating Modes
IDT PES12NT12G2 Device Overview Notes PCI Express Ports SerDes GPIO GPIO Controller Stack 0 Module Master Master SMBus SMBus Interface Switch Core Slave Slave SMBus SMBus Interface Stack 2 Stack 3 Module Reset and Boot Reset Configuration SerDes SerDes Controller Vector PCI Express Ports Figure 1.1 PES12NT12G2 Block Diagram...
Page 40 IDT PES12NT12G2 Device Overview Notes PES12NT12G2 ports support the following port operating modes. – Disabled – Unattached – Upstream switch port (i.e., upstream PCI-to-PCI bridge) – Downstream switch port (i.e., downstream PCI-to-PCI bridge) – Upstream switch port with DMA function –...
Page 41 IDT PES12NT12G2 Device Overview Notes PCI Express Link Port Physical Layer Data Link Layer Bridge Function Function Switch Virtual Bus Interconnect Figure 1.2 Logical Representation of a Port with PCI-to-PCI bridge, NT, and DMA Functions Not all ports support all port operating modes. The following applies. –...
Page 42: Switch Partitioning
IDT PES12NT12G2 Device Overview Notes Port Support Port Operating Mode 10 11 16 17 18 19 Disabled • • • • • • • • • • • • Unattached • • • • • • • • • • •...
Page 43: Figure 1.4 Partitionable Pci Express Switch
IDT PES12NT12G2 Device Overview Notes The PES12NT12G2 is a partitionable PCI Express switch. This means that in addition to operating as a standard PCI Express switch, PES12NT12G2 ports may be partitioned into groups that logically operate as completely independent PCI Express switches. Figure 1.4 illustrates a three partition switch configuration. Partition 1 Partition 2 Partition 3...
Page 44: Non-Transparent Operation
IDT PES12NT12G2 Device Overview Non-Transparent Operation Notes The PCI architecture defines a hierarchy of buses interconnected by PCI-to-PCI bridges. This hierarchy forms a tree and is referred to as a PCI domain. – A PCI domain consists of a single memory address space, I/O address space, and ID address space.
Page 45: Figure 1.6 Generalized Multi-Port Non-Transparent Interconnect
IDT PES12NT12G2 Device Overview Notes Non-transparent operation is related to the concept of switch partitioning in that the non-transparent interconnect allows switching between multiple switch partitions, each of which is associated with a sepa- rate PCIe domain. PCIe PCIe PCIe PCIe Domain 0 Domain 1...
Page 46: Figure 1.7 Architectural Approaches For Integrating Non-Transparency Into A Pci Express Switch
IDT PES12NT12G2 Device Overview Notes Upstream Port Non-Transparent Upstream Upstream Bridge Port Port Port Virtual PCI Bus Non- Bridge Transparent Endpoint Bridge Endpoint Interconnect Bridge Bridge Virtual PCI Bus Virtual PCI Bus Bridge Bridge Endpoint Endpoint Non- Non- Transparent Transparent Interconnect Interconnect Endpoint...
Page 47: Figure 1.8 Non-Transparent Switch With Non-Transparency Between Partitions
IDT PES12NT12G2 Device Overview Notes Upstream Upstream Port Port P2 P P2 P Non- Transparent Bridge Endpoint Endpoint Bridge Interconnect Partition 0 – Virtual PCI Bus Partition 1 – Virtual PCI Bus P2 P P2 P P2 P P2 P Bridge Bridge Bridge...
Page 48: Dma Operation
IDT PES12NT12G2 Device Overview DMA Operation Notes The PES12NT12G2 supports two Direct Memory Access controller (DMA) functions. Each DMA func- tion appears as a PCI Express endpoint in the PCI Express hierarchy, located in a switch partition’s upstream port. In each partition, the operating mode of the switch’s upstream port determines if this port contains a DMA function.
Page 49: Figure 1.10 Switch Partition With Dma Function
IDT PES12NT12G2 Device Overview Notes Upstream Port Bridge Function Virtual PCI Bus Bridge Bridge Bridge Bridge Bridge Downstream Ports Figure 1.10 Switch Partition with DMA Function Figure 1.11 shows the logical view of two switch partitions interconnected via an NTB, with a DMA func- tion in the upstream port of one partition.
Page 50: Dynamic Reconfiguration And Failover
IDT PES12NT12G2 Device Overview Notes Upstream Upstream Port Port Non-Transparent Function Bridge Endpoint Endpoint Interconnect Partition 0 – Virtual PCI Bus Bridge Bridge Downstream Ports Figure 1.11 Two Switch Partitions Interconnected by an NTB, with DMA in One Partition Upstream Upstream Port Port...
Page 51: Figure 1.13 Non-Transparent Switch Failover Usage
IDT PES12NT12G2 Device Overview Notes or SMBus master, or initiated by hardware as the result of a failover event. The switch supports four failover configuration structures. Each configuration structure may be independently configured to initiate a failover event on: – a configuration register write, –...
Page 52: Switch Events
IDT PES12NT12G2 Device Overview Switch Events Notes In a multi-partition switch, such as the PES12NT12G2, a need may exist to signal the occurrence of certain events that occur within a partition to agents (e.g., a PCI Express function) in other partitions. For example, in a switch configuration with two or more partitions, the occurrence of a hot reset in a partition is an event that may be signaled to the root-complex in other partitions or to a switch management agent connected to yet another partition.
Page 53: Multicasting And Non-Transparent Multicasting
IDT PES12NT12G2 Device Overview Notes Global signal events allow an agent in a partition to issue a signal to agents in other partitions. A global signal is initiated when an agent in a partition writes to a specific register in the upstream port of the switch partition.
Page 54: Figure 1.16 Example Of Non Transparent Multicast
IDT PES12NT12G2 Device Overview Notes Figure 1.16 shows an example of an NT multicast transfer. In this example, a TLP received by an NT endpoint is NT multicasted and transmitted by ports located in other partitions. Such a configuration may be found in multiprocessor systems in which multiple CPUs need to exchange data or state associated with a distributed computation.
Page 55: Clocking
Chapter 2 Clocking ® Overview Notes Figure 2.1 provides a logical representation of the PES12NT12G2 clocking architecture. The switch has two differential global reference clock input (GCLK) pairs as well as several differential reference clock inputs (PxCLK) used for local port clocking. The differential global reference clock input (GCLK) is driven into the device on the GCLKP[1:0] and GCLKN[1:0] pins.
Page 56: Port Clocking Modes
IDT Clocking SerDes SerDes SerDes SerDes Quad Quad Quad Quad Ports Ports Ports Ports 8 to 11 0 & 1 16 to 19 2 & 3 Switch Core GCLK Figure 2.1 Logical Representation of PES12NT12G2 Clocking Architecture Port Clocking Modes Port clocking refers to the clock that a port uses to receive and transmit serial data.
Page 57: Global Clocked Mode
IDT Clocking Global Clocked Mode Notes A port in global clocked mode uses the global reference clock (GCLK) input for receiving and transmit- ting serial data. The port clock (PxCLK) associated with such a port (if any) is unused by the port. If no other port uses that same PxCLK, the PxCLK pins should be connected to Vss on the system board.
Page 58: Local Port Clocked Mode
IDT Clocking Local Port Clocked Mode Notes A port in local port clocked mode uses a dedicated port clock (PxCLK) input for receiving and transmit- ting serial data. Table 2.2 lists the ports and the PxCLK used by each. PxCLK used when port Ports operates in Port Clocked Mode...
Page 59: Support For Spread Spectrum Clocking (Ssc)
IDT Clocking Notes Figure 2.5 shows the clock connection between a PES12NT12G2 port and it’s link partner, when the switch port operates in local port clocked mode with a non-common clock configuration. Switch GCLK Clock Generator Port PxCLK Clock Generator Clock Link Partner Generator...
Page 60: Port Clocking Mode Selection
IDT Clocking Notes Nominal PxCLK Effective Allowed PxCLK PxCLK GCLK Frequency Modulation Frequency Frequency 100 MHz + 300ppm +0 / - 5000ppm 100 Mhz +300 / - 100 Mhz + / - 4700ppm 300ppm 100 MHz - 300ppm +0 / - 5000ppm 100 Mhz -300 / - 100 Mhz + / - 5300ppm...
Page 61: Table 2.5 Initial Port Clocking Mode And Slot Clock Configuration State
IDT Clocking Notes CLKMODE[1:0] Port Port Value in Boot Port 0 Port 0 [9:16,11:8, [19:16,11:8,3:1] Configuration Clocking Mode SCLK 3:1] Clocking Mode Vector SCLK Global Clocked Global Clocked (non-common (non-common clocked) clocked) Global Clocked Global Clocked (common (non-common clocked) clocked) Global Clocked Global Clocked (non-common...
Page 62: System Clocking Configurations
IDT Clocking System Clocking Configurations Based on the requirements outlined in the sections above, Table 2.7 summarizes valid system clocking configurations (highlighted in green). Invalid system configurations are highlighted in red. PES12NT12G2 Port Configuration Link Valid Port Local Partner Notes Global Config.
Page 63: Reset And Initialization
Chapter 3 Reset and Initialization ® Overview Notes This chapter describes the PES12NT12G2 resets and initialization. There are two classes of switch resets. The first is a switch fundamental reset which is the reset used to initialize the entire device. The second class is referred to as partition resets.
Page 64: Switch Fundamental Reset
IDT Reset and Initialization Switch Fundamental Reset Notes A switch fundamental reset may be cold or warm. A cold switch fundamental reset occurs following a device being powered-on and assertion of the global reset (PERSTN) signal. A warm switch fundamental reset occurs when a switch fundamental reset is initiated while power remains applied.
Page 65: Figure 3.1 Switch Fundamental Reset With Serial Eeprom Initialization
IDT Reset and Initialization Notes – When serial EEPROM initialization completes, the EEPROM Done (EEPROMDONE) bit in the SMBUSSTS register is set and the switch’s ports start processing configuration requests normally, unless the RSTHALT bit in the SWCTL register is set. If serial EEPROM initialization completes with an error, the RSTHALT bit in the SWCTL register is set as described in section Initialization from Serial EEPROM on page 12-3.
Page 66: Boot Configuration Vector
IDT Reset and Initialization Notes The operation of a switch fundamental reset using RSTHALT is illustrated in Figure 3.2. Stable Stable Power GCLK GCLK* > 100ns PERSTN < 100 ms ~285 μs ~2 μs Link Ready SerDes PLL Reset & Lock Link Training CDR Lock RSTHALT...
Page 67: Stack Configuration
IDT Reset and Initialization Notes May Be Signal Name/Description Overridden GCLKFSEL Global Clock Frequency Select. These pins specify the frequency of the GCLKP and GCLKN sig- nals. CLKMODE[1:0] Clock Mode. These pins specify the clocking mode used by switch ports. See Table 2.5 for a definition of the encoding of these signals.
Page 68: Table 3.3 Ports In Each Stack
IDT Reset and Initialization Notes Ports Associated with Stack the Stack Stack 0 0, 1, 2, 3 (non-mergeable) Stack 2 8, 9, 10, 11 Stack 3 16, 17, 18, 19 Table 3.3 Ports in Each Stack Stack 0 can only be configured as four x1 ports. Stacks 2 and 3 may each be configured as one x4 port, two x2 ports, or four x1 ports and combinations in between.
Page 69: Static Configuration Of A Stack
IDT Reset and Initialization Notes STKCFG Field in the Stack Configuration STK3CFG Register Binary 0b00001 0b00011 0b01000 0b01001 0b01010 Others Reserved Table 3.6 Possible Configurations for Stack 3 Depending on the stack configuration, some ports in the stack may be ‘activated’ and others ‘de-acti- vated’.
Page 70: Dynamic Reconfiguration Of A Stack Via Eeprom / Smbus
IDT Reset and Initialization Dynamic Reconfiguration of a Stack via EEPROM / SMBus Notes In addition to static configuration as described above, each stack may be reconfigured via the EEPROM or SMBus slave interface during the switch fundamental reset sequence (i.e., at the EEPROM loading step or via the slave SMBus interface when the ports are in quasi-reset state Dynamic reconfiguration of a stack requires the following procedure.
Page 71: Table 3.8 Switch Mode Dependent Register Initialization
IDT Reset and Initialization Notes The only exception to this rule are the reduced latency modes (i.e., “Single partition with reduced latency” and “Single partition with Serial EEPROM initialization and reduced latency”). These modes represent a single partition switch configuration in which partition state and port modes (see Chapter 5, Switch Partition and Port Configuration) can’t be modified, except for port device number in downstream ports .
Page 72: Partition Resets
IDT Reset and Initialization Partition Resets Notes A partition reset is a reset that is associated with a specific switch partition. The reset has an effect only on those functions and ports associated with that switch partition. It has no effect on the operation of other switch partitions, ports in other switch partitions, or logic not associated with a switch partition (e.g., master SMBus, slave SMBus).
Page 73: Partition Hot Reset
IDT Reset and Initialization Partition Hot Reset Notes A partition hot reset is initiated by any of the following events. – Reception of TS1 ordered-sets on the partition’s upstream port indicating a hot reset. – Data link layer of the partition’s upstream port indicates a DL_Down status. The only exception case is a DL_Down caused by the upstream port’s link transitioning to L2/L3 Ready state (refer to section Link States on page 7-9).
Page 74: Partition Upstream Secondary Bus Reset
IDT Reset and Initialization Partition Upstream Secondary Bus Reset Notes A partition upstream secondary bus reset is initiated by any of the following events. – A one is written to the Secondary Bus Reset (SRESET) bit in the Bridge Control (BCTL) register of the PCI-to-PCI bridge function in the partition’s upstream switch port When an upstream secondary bus reset occurs, the following sequence of actions take place on logic associated with the affected partition.
Page 75: Port Mode Change Reset
IDT Reset and Initialization Notes The operation of other downstream switch ports in this and other partitions is unaffected by a partition downstream secondary bus reset. During a partition downstream secondary bus reset, type 0 configuration read and write transactions that target the downstream switch port complete normally. During a partition downstream secondary bus reset, all TLPs destined to the secondary side of the downstream switch port’s PCI-to-PCI bridge are treated as unsupported requests.
Page 76 IDT Reset and Initialization Notes PES12NT12G2 User Manual 3 - 14 July 10, 2013...
Page 77: Switch Core
Chapter 4 Switch Core ® Overview Notes This chapter provides a detailed description of the PES12NT12G2’s switch core. As shown in section Architectural Overview on page 1-2, the switch core interconnects three stacks and two DMA modules. The three stacks are numbered 0, 2, and 3. Stack 0 is configured as four x1 non-mergeable ports. Stacks 2 and 3 may each be configured with a maximum of four x1 ports.
Page 78: Ingress Buffer
IDT Switch Core Notes Switch Core Port 0 IFB Port 0 EFB Stack 0 Stack 0 Port 1 IFB Port 1 EFB Ingress Egress Datapath Datapath Port 2 IFB Port 2 EFB Port 3 IFB Port 3 EFB Port 8 EFB Port 8 IFB Stack 2 Port 9 EFB...
Page 79: Egress Buffer
IDT Switch Core Notes The IFB consists of three queues. These queues are the posted transaction queue (PT queue), the non- posted transaction queue (NP queue), and the completion transaction queue (CP queue). The queues for the IFB are implemented using a descriptor memory and a data memory. The size of a port’s IFB depends on the port’s maximum link width as determined by the configuration of the stack associated with the port.
Page 80: Crossbar Interconnect
IDT Switch Core Notes Stack Total Size and Limitations Mode Queue (per-port) Posted 8192 Bytes and up to 128 TLPs Merged Non Posted 2048 Bytes and up to 128 TLPs Completion 8192 Bytes and up to 128 TLPs Posted 4096 Bytes and up to 64 TLPs Bifurcated Non Posted 1024 Bytes and up to 64 TLPs...
Page 81: Virtual Channel Support
IDT Switch Core Notes sustaining full bandwidth throughput on a x4 Gen2 link and may be shared by four x1 ports, two x2 ports, or one x4 port. Two memory modules are used for an x8 Gen2 port. The PES12NT12G2 switch core contains eight ingress memory modules and eight egress memory modules as shown in Figure 4.1.
Page 82: Packet Ordering
IDT Switch Core Packet Ordering Notes The PCI Express Base Specification 2.1 contains packet ordering rules to ensure the producer/ consumer model is honored across a PCI Express hierarchy and to prevent deadlocks. – The switch honors the strict and relaxed ordering rules defined in the PCI Express Base Specifi- cation.
Page 83: Figure 4.2 Architectural Model Of Arbitration
IDT Switch Core Notes Port 0 IFB Function 0 Port 0 Arbitration VC 0 VC Capability Structure Port 0 EFB Port 1 IFB Port Arbiter VC 0 VC 0 Function 0 Port 12 Arbitration VC Capability Structure Port 12 EFB Port Arbiter VC 0 Port 0 , Function 0...
Page 84 IDT Switch Core Notes Switch ports in this device support port arbitration using hardware fixed round-robin. As such, the port’s VC Capability Structure indicates support for a hardware-fixed algorithm only (i.e., round-robin). Hardware Fixed Round-Robin Arbitration By default, all ports are programmed for hardware fixed round-robin port arbitration. A port operates in this mode unless it is configured for WRR arbitration as discussed in section Proprietary Weighted Round Robin (WRR) Arbitration below.
Page 85: Cut-Through Routing
IDT Switch Core Notes As another example, if the DMA engine located in function 2 of port 0 is active, the P24IC field of all ports out of which a DMA may issue traffic must not be set to 0x0. This includes ports in the same logical partition as the DMA, or ports in other partitions (i.e., when the DMA transmits packets across the NT bridge or NT multicast).
Page 86: Table 4.5 Conditions For Cut-Through Transfers
IDT Switch Core Notes Ingress Egress Ingress Egress Link Link Conditions for Link Link Speed Speed Cut-Through Width Width (GT/s) (GT/s) x8, x4, x2, x1 Always x4, x2, x1 Always At least 50% of packet is in IFB x4, x2, x1 Always At least 50% of packet is in IFB x2, x1...
Page 87: Request Metering
IDT Switch Core Notes Ingress Egress Ingress Egress Link Link Conditions for Link Link Speed Speed Cut-Through Width Width (GT/s) (GT/s) x8, x4, x2, x1 Always x8, x4, x2, x1 Always x8, x4, x2, x1 Always At least 50% of packet is in IFB x4, x2, x1 Always At least 50% of packet is in IFB...
Page 88: Figure 4.3 Pci Express Switch Static Rate Mismatch
IDT Switch Core Notes If read requests are injected sporadically or at a low rate, then buffering within the switch may be used to accommodate short lived contention and allow completions to endpoints to proceed without interfering. If read requests are injected at a high rate, then no amount of buffering in the switch will prevent completions from interfering.
Page 89: Operation
IDT Switch Core Notes Request Request Request Time (a) Request Injection without Request Metering Estimate of Request 2 Estimate of Request 1 Completion Transfer Time Completion Transfer Time Request Request Request Time (b) Request Injection with Request Metering Figure 4.4 PCI Express Switch Static Rate Mismatch The request metering implementation in the switch makes a number of simplifying assumptions that may or may not be true in all systems.
Page 90: Completion Size Estimation
IDT Switch Core Notes The Decrement Value Adjustment (DVADJ) field represents a 1:4:11 number (i.e., a sign-magnitude fixed-point number with 4 integer bits and 11 fractional bits). The signed nature of the DVADJ field provides fine grain programmable adjustment of the value by which the counter is decremented. When the sum of the decrement value plus DVADJ results in a value less than or equal to zero, the hardware ignores DVADJ and uses the decrement value.
Page 91: Figure 4.6 Non-Posted Read Request Completion Size Estimate Computation
IDT Switch Core Notes Non-Posted Reads The completion size estimate is based on the Length field in the read request header and is computed as shown in Figure 4.6. All arithmetic in this section is performed using an implicit 0:13:3 representation and all values are implicitly converted to this value.
Page 92: Internal Errors
IDT Switch Core Internal Errors Notes Internal errors are errors which are associated with a PCI Express interface, which occur within a component, and which may not be attributable to a packet or event on the PCI Express interface itself or on behalf of transactions initiated on PCI Express.
Page 93: Switch Core Time-Outs
IDT Switch Core Notes Each internal error status bit has an associated severity bit in the Internal Error Severity (IERRORSEV0/ 1) registers. When an unmasked internal error is detected, the error is reported as dictated by the corre- sponding severity bit (i.e., either an uncorrectable internal error or a correctable internal error). When an uncorrectable or correctable internal error is reported, the corresponding AER status bit is set and processed as dictated by the PCI Express Base Specification.
Page 94: Memory Secded Ecc Protection
IDT Switch Core Notes set in the Internal Error Reporting Status 0 (IERRORSTS0) register. If during processing of a TLP with broadcast or multicast routing a switch core time-out occurs, then the switch core will abort processing of the TLP. This may result in the broadcast TLP being transmitted on some but not all destination ports. For ports that contain a DMA function, the DMA has separate switch time out controls.
Page 95: Reporting Of Port Aer Errors As Internal Errors
IDT Switch Core Notes As the TLP flows through the switch, its alignment or contents may be modified. In all such cases, parity is updated and not recomputed. Hence, any error that occurs is propagated and not masked by a parity regeneration.
Page 96 IDT Switch Core Notes Each port is capable of notifying the detection of an AER error to other ports. Each port has an internal non-software visible register named Port AER Status (PAERSTS) which provides a gathering point for combined AER correctable and uncorrectable errors of all functions (e.g., PCI-to-PCI bridge, NT, and DMA) in the port.
Page 97: Figure 4.8 Reporting Of Port Aer Errors As Internal Errors
IDT Switch Core Notes Switch Port 1 PCI-to-PCI Bridge Function Internal Error Detection Logic Port 0 PAERMSK Port 2 Port N PAERSTS (not exposed to software) Internal Error AER Error AER Error AER Error Detection Logic Detection Logic Detection Logic Detection Logic (internal errors (Function 0)
Page 98 IDT Switch Core Notes PES12NT12G2 User Manual 4 - 22 July 10, 2013...
Page 99: Switch Partition And Port Configuration
Chapter 5 Switch Partition and Port Configuration ® Overview Notes The PES12NT12G2 supports up to 4 active switch partitions. Each switch partition represents an inde- pendent PCI Express hierarchy whose operation is independent of other switch partitions. A port may be configured to operate in one of the following modes.
Page 100: Partition Configuration
IDT Switch Partition and Port Configuration Notes • NT with DMA function – A downstream switch port is a port configured to operate in downstream switch port mode and attached to a partition. – An upstream switch port is an upstream port with a PCI-to-PCI bridge function (i.e., a port in upstream switch port mode, upstream switch port with DMA function mode, upstream switch port with NT function mode, or upstream switch port with NT and DMA functions mode).
Page 101: Partition State
IDT Switch Partition and Port Configuration Notes • The completion may be expected or unexpected depending on the configuration of the func- tion at the time the completion is received. – The upstream switch port is allowed to enter and exit L0s and L1 ASPM state without regard to the ASPM state of a downstream switch port (i.e., since there are no downstream switch ports, they play no role in determining when an upstream port enters or exists a low power ASPM state).
Page 102: Partition State Change
IDT Switch Partition and Port Configuration Notes The partition fundamental reset condition is considered to persist as long as the STATE field in the SWPARTxCTL register remains in the fundamental reset state. No hardware-initiated hot reset is possible in the partition (e.g., a link-down in the partition’s upstream port (if any) does not cause a hot reset). See Table 3.1 for details on reset precedence.
Page 103: Switch Ports
IDT Switch Partition and Port Configuration Notes Partition State Change via EEPROM When modifying the state of a partition via the serial EEPROM, the following recommendations and requirements apply. Prior to modifying the state of a partition, it is required that the following proprietary timer registers be set to 0x0.
Page 104: Figure 5.2 Logical Representation Of A Port With Pci-To-Pci Bridge, Nt, And Dma Functions
IDT Switch Partition and Port Configuration Notes A port in an operational mode is associated to the partition specified by the Switch Partition (SWPART) field in the corresponding Switch Port Control (SWPORTxCTL) register. The following switch port modes are considered operational modes. –...
Page 105: Table 5.1 Port Functions For Each Port Operating Mode
IDT Switch Partition and Port Configuration Notes Regardless of a port’s operating mode, all registers in all functions of the port remain accessible via the switch’s global address space, via the SMBus slave interface, or via serial EEPROM (see Chapter 19, Register Organization).
Page 106 IDT Switch Partition and Port Configuration Notes A port is not associated with any switch partition if the disabled port mode is due to the Port Mode (MODE) field in the Switch Port Control (SWPORTxCTL) register being set to Disabled. Since the port is not associated with a switch partition in this mode, the port is unaffected by the state of any switch partition, and vice-versa.
Page 107 IDT Switch Partition and Port Configuration Notes The port responds to received TLPs as follows: – All received PCI Express configuration requests that do not target function 0 are completed with a configuration-request-retry-status completion. The intent of this requirement is to prevent stan- dard enumeration software from detecting the existence of port functions which may not be present in the port after the partition is configured.
Page 108 IDT Switch Partition and Port Configuration Notes • Since the link operates as an upstream port (i.e., downstream component), an automatic speed change is not initiated when the link enters L0. Automatic speed change may be enabled by modifying the value of the Initial Link Speed Change Control (ILSCC) bit in the PCI-to-PCI bridge function’s Phy Link Configuration 0 (PHYLCFG0) register.
Page 109 IDT Switch Partition and Port Configuration Notes Since the link operates as an upstream port (i.e., downstream component), an automatic speed change is not initiated when the link enters L0. Automatic speed change may be enabled by modifying the value of the Initial Link Speed Change Control (ILSCC) bit in the PCI-to-PCI bridge function’s Phy Link Configuration 0 (PHYLCFG0) register.
Page 110 IDT Switch Partition and Port Configuration Notes • Automatic speed change may be enabled by modifying the value of the Initial Link Speed Change Control (ILSCC) bit in the PCI-to-PCI bridge function’s Phy Link Configuration 0 (PHYLCFG0) register. – PCI Express requests that do not target functions 0, 1, 2 are completed with unsupported request status by the port.
Page 111: Port Operating Mode Change
IDT Switch Partition and Port Configuration Notes • The negated value of PxAIN, PxILOCKP, PxPEP, PxPIN, and PxRSTN is determined as shown in Table 11.2. PCI Express requests that do not target function 0 or function 2 are completed with unsupported request status by the port. The completion has a value of all zeroes in the function number field of the completer ID.
Page 112: Table 5.2 Port Operating Mode Changes Supported By The Switch
IDT Switch Partition and Port Configuration Notes US + US + US + NT + NT + UNATTACHED (UN) DISABLED (DIS) UPSTREAM (US) US + NT FROM US + DMA NT + DMA US + NT + DMA Table 5.2 Port Operating Mode Changes Supported by the Switch Note that the port operating mode changes shown as not supported in Table 5.2 only apply for direct transitions between the operating modes.
Page 113: Common Operating Mode Change Behavior
IDT Switch Partition and Port Configuration Notes Where, – SEDELAY is the Side Effect Delay Timer (defaults to 1 ms). – POMCDELAY is the Port Operating Mode Change Timer (defaults to 1 ms) – RDRAINDELAY is the Reset Drain Delay Timer (defaults to 0.25 ms) •...
Page 114 IDT Switch Partition and Port Configuration Notes A port operating mode change that is caused only by a device number change is logically viewed as a source partition removal, followed by a device number change, followed by a destination partition addition to the same partition.
Page 115 IDT Switch Partition and Port Configuration Notes Routing Removing a port from a partition results in the corresponding invalidation of routes to all functions of that port. For example, removing a downstream switch port from a partition causes all other downstream switch ports in the partition, as well as the upstream port’s PCI-to-PCI bridge function, to invalidate routes to the moved downstream switch port.
Page 116 IDT Switch Partition and Port Configuration Notes PME Synchronization Removing a port from a partition has the effect of removing it from participation in PME synchronization associated with the source partition. If PME synchronization is in progress, then PME synchronization completes before the port (upstream or downstream) is removed from the partition.
Page 117 IDT Switch Partition and Port Configuration Notes Partition Upstream Secondary Bus Reset See section Partition Upstream Secondary Bus Reset on page 3-12 for an overview of partition upstream secondary bus reset. The addition of an upstream switch port whose SRESET bit in the BCTL register of the port’s PCI-to-PCI bridge function is set, has the effect of initiating a partition upstream secondary bus reset.
Page 118 IDT Switch Partition and Port Configuration Notes Upstream switch port addition A switch partition must initiate an exit from L0s on the transmitters of all downstream switch ports asso- ciated with the partition if it detects an exit from L0s on the receiver of its upstream switch port. See the PCI Express Base Specification for details.
Page 119: No Action Mode Change Behavior
IDT Switch Partition and Port Configuration Notes INTx Interrupt Signaling Adding an upstream switch port to a partition causes the PCI-to-PCI bridge function in the upstream switch port to adopt the aggregated interrupt state of the downstream switch ports associated with the desti- nation partition.
Page 120: Reset Mode Change Behavior
IDT Switch Partition and Port Configuration Reset Mode Change Behavior Notes Modifying the operating mode of a port when the OMA field is set to port reset has the following behavior in addition to that specified by the common operating mode change behavior: –...
Page 121: Partition Reconfiguration Latency
IDT Switch Partition and Port Configuration Notes A failover event may also trigger a modification in the state of a partition. When the Failover Enable (FEN) bit is set in the Switch Partition Failover Control (SWPARTxCTL) register, automatic failover reconfig- uration is enabled.
Page 122 IDT Switch Partition and Port Configuration Notes Finally, if the reconfiguration is done by a switch management agent, the agent can coordinate and notify the reconfiguration using the global signals event mechanism described in section Global Signals on page 16-4. PES12NT12G2 User Manual 5 - 24 July 10, 2013...
Page 123: Failover
Chapter 6 Failover ® Overview Notes The PES12NT12G2 supports a flexible failover mechanism that allows the construction of highly-avail- able systems. The failover mechanism can be used to automatically reconfigure switch partitions (as described in section Partition Reconfiguration and Failover on page 5-22) upon detection of a pre-defined trigger.As shown in Figure 6.1, there is a clear distinction in the switch between the policy used to trigger a failover and the reconfiguration.
Page 124: Software Initiated Failover
IDT Failover Notes The following sections describe each of these policies. In most systems it is expected that a failover capability will only use one policy at a time. While enabling multiple policies in a single failover capability is not prohibited, care must be exercised to ensure that only one failover occurs at a time. If a second failover is triggered while an earlier failover is in progress, then the behavior is undefined.
Page 125 IDT Failover Notes When a failover is triggered, the type of failover is determined by the state of the Failover Mode (FMODE) field in the corresponding Failover Capability Status (FCAPxSTS) register. – If the current failover mode is primary, then a secondary failover is triggered. –...
Page 126 IDT Failover Notes PES12NT12G2 User Manual 6 - 4 July 10, 2013...
Page 127: Link Operation
Chapter 7 Link Operation ® Overview Notes Link operation in the PES12NT12G2 switch adheres to the PCI Express Base Specification Revision 2.1, supporting speeds of 2.5 GT/s and 5.0 GT/s. This chapter does not describe the controls related to the Serializer-Deserializer (SerDes) block associated with each port.
Page 128: Polarity Inversion
IDT Link Operation Polarity Inversion Notes Each port of this switch supports automatic polarity inversion as required by the PCI Express Base Specification. Polarity inversion is a function of the receiver and not the transmitter. The transmitter never inverts its data. During link training, the receiver examines symbols 6 through 15 of the TS1 and TS2 ordered sets for inversion of the PExRP[n] and PExRN[n] signals.
Page 129: Figure 7.2 Lane Reversal For Highest Achievable Link Width Of X4
IDT Link Operation Notes PExRP[n] lane 0 PExRP[n] lane 3 PExRP[n+1] lane 1 PExRP[n+1] lane 2 Switch Switch PExRP[n+2] lane 2 PExRP[n+2] lane 1 PExRP[n+3] lane 3 PExRP[n+3] lane 0 (a) Port trains to x4 without lane reversal (b) Port trains to x4 with lane reversal PExRP[n] lane 0 PExRP[n]...
Page 130: Link Width Negotiation
IDT Link Operation Notes PExRP[n] lane 7 PExRP[n] lane 0 PExRP[n+1] lane 6 PExRP[n+1] lane 1 PExRP[n+2] lane 5 PExRP[n+2] lane 2 PExRP[n+3] lane 4 PExRP[n+3] lane 3 Switch Switch PExRP[n+4] lane 3 PExRP[n+4] lane 4 PExRP[n+5] lane 2 PExRP[n+5] lane 5 PExRP[n+6] lane 1...
Page 131: Link Width Negotiation In The Presence Of Bad Lanes
IDT Link Operation Notes The actual link width is determined dynamically during link training. Ports limited to a maximum link width of x8 are capable of negotiating to a x8, x4, x2, or x1 link width. The actual negotiated width of a link may be determined from the Negotiated Link Width (NLW) field in the corresponding port’s PCI Express Link Status (PCIELSTS) register.
Page 132: Dynamic Link Width Reconfiguration In The Pes12Nt12G2
IDT Link Operation Notes Software may be notified of link width reconfiguration via the link bandwidth notification mechanism described in the PCI Express Base Specification. This mechanism is enabled by setting the Link Bandwidth Management Interrupt Enable (LBWINTEN) bit in the PCIELCTL register of switch downstream switch ports.
Page 133: Link Speed Negotiation In The Pes12Nt12G2
IDT Link Operation Notes It is the responsibility of the upstream component of the link (i.e., switch downstream switch ports) to keep the link at the target link speed or at the highest common speed supported by both components of the link, whichever is lower.
Page 134: Software Management Of Link Speed
IDT Link Operation Notes When operating at 5.0 GT/s, a PES12NT12G2 port initiates a link speed downgrade in the following cases: – When the PHY layer cannot achieve reliable operation at the higher speed. In this case, the PES12NT12G2 port continues to support the higher speed in the training-sets it transmits during link training.
Page 135: Link Retraining
IDT Link Operation Notes For downstream switch ports, the Link Bandwidth Management Status (LBWSTS) bit in the PCIELSTS register is set when the link speed is changed due to the following reasons: – Link speed downgrade initiated by a switch port when the PHY layer cannot achieve reliable oper- ation at the higher speed.
Page 136: Link Down Handling
IDT Link Operation Notes • May be automatically entered (i.e., ASPM) or directed by software by placing the device in the state – L2/L3 Ready • The L2/L3 state is entered after the acknowledgement of a Power Management Event Turn Off (PME_Turn_Off) Message.
Page 137: Slot Power Limit Support
IDT Link Operation Notes When a downstream switch port’s data-link indicates a DL_Down status, the following occurs: – All TLPs queued in the port’s ingress frame buffer (IFB) are silently discarded. – All TLPs queued in the port’s replay buffer (EFB) are silently discarded. –...
Page 138: Downstream Switch Port
IDT Link Operation Downstream Switch Port Notes A Set_Slot_Power_Limit message is generated and transmitted by downstream switch ports when either of the following events occur: – A configuration write is performed to the corresponding PCIESCAP register when the link associ- ated with the downstream switch port is up.
Page 139: L1 Aspm
IDT Link Operation Notes A port configured in NT function mode or NT with DMA function mode initiates L0s entry when all of the conditions listed below are met: – L0s ASPM is enabled via the PCIELCTL register of all functions in the port. –...
Page 140 IDT Link Operation Notes The PES12NT12G2 upstream ports request entry into L1 based on the criteria defined below. The L1 entry conditions must be met for 1 ms before the upstream port transitions the link to the L1 state. If these conditions are met and the link is in the L0 or L0s states, then the hardware will request a transition to the L1 state from its link partner.
Page 141 IDT Link Operation Notes A port configured in downstream switch port mode initiates exit from L1 when either of the conditions listed below is met: – The port has a TLP scheduled for transmission on the link. – The upstream port in the switch partition has initiated exit from L1. The latency between the upstream port’s initiated exit from L1 and the downstream switch port’s initiated exit from L1 must not exceed 1 µs.
Page 142: Link Status
IDT Link Operation Notes The L1ASPMRTC register is located in the proprietary port-specific registers located in the PCI-to-PCI bridge function’s configuration space (see section Proprietary Port-Specific Registers in the PCI-to-PCI Bridge Function on page 19-11). This timer may be programmed from the nano-second range (i.e., 100 ns) up to the micro-second range (i.e., 64 µs).
Page 143: Crosslink
IDT Link Operation Crosslink Notes PES12NT12G2 ports support the optional crosslink capability specified in the PCI Express Base Speci- fication. Per this specification, a crosslink is established between two downstream switch ports or two upstream ports. The device’s ports are capable of establishing crosslink with any link partner, including another switch port.
Page 144: Gen 1 Compatibility Mode
IDT Link Operation Notes If a higher layer directs the port to disable the link (i.e., the Link Disable (LDIS) bit is set in the port’s PCIELCTL register), the physical layer enters the recovery state and proceeds to the disabled state, as specified in the PCI Express Base Specification. The physical layer responds to the reception of training sets with the disabled bit set by transitioning to the disabled state as specified in the PCI Express Base Specification.
Page 145: Serdes
Chapter 8 SerDes ® Overview Notes This chapter describes the controllability of the Serialiazer-Deserializer (SerDes) block associated with each PES12NT12G2 port. A SerDes block is composed of the serializing/deserializing logic for four PCI Express lanes (i.e., a SerDes “quad”), plus a central unit that controls the quad as a whole. This central unit is called CMU, and contains functionality such as a PLL to generate a high-speed clock used by each lane, initialization of the quad, etc.
Page 146: Serdes Transmitter Controls
IDT SerDes Notes SerDes Quad 1 SerDes Quad 0 Stack 0 Configuration Lane3 Lane 2 Lane 1 Lane 0 Lane3 Lane 2 Lane 1 Lane 0 x1, x1, x1, x1 — Port 3 — Port 2 — Port 1 — Port 0 —...
Page 147: Driver Voltage Level And Amplitude Boost
IDT SerDes Driver Voltage Level and Amplitude Boost Notes The PCI Express Base Specification requires that each port support the ‘transmit margining’ feature. This feature allows the selection of several voltage settings across the link and is intended for compliance testing and debug.
Page 148: Programming Of Serdes Controls
IDT SerDes Notes Receiver equalization can be controlled on a per-lane basis. Each SerDes lane contains a receiver equalization circuit. This circuit is a multi-stage programmable amplifier, where each stage is a peaking equalizer with a different center frequency and programmable gain. Varying amounts of gain may be applied depending on the overall frequency response of the channel loss.
Page 149: Serdes Transmitter Control Registers
IDT SerDes Notes – As another example, when port 8 is configured as a x2 port, it is associated with SerDes quad 4, lanes 0 and 1 (see Table 8.2). If the TM field in the port’s PCIELCTL2 register is set to ‘Normal Operating Range’, then the S[4]TXLCTL0 and S[4]TXLCTL1 registers control the operating voltage of the port’s SerDes lanes.
Page 150: Table 8.4 Serdes Transmit Level Controls In The S[X]Txlctl0 And S[X]Txlctl1 Registers
IDT SerDes Notes Relevant Relevant fields in PHY Operation Mode fields in S[x]TXLCTL1 S[x]TXLCTL0 Fine De- Drive Level / Voltage Data emphasis Fine De-emphasis Swing Rate emphasis Control Control Full-Swing 2.5 GT/s -3.5 dB FDC_FS3DBG1 TDVL_FS3DBG1 / CDC_FS3DBG1 Full-Swing 5.0 GT/s -3.5 dB FDC_FS3DBG2 TDVL_FS3DBG2 /...
Page 151: Table 8.6 Serdes Transmit Driver Settings In Gen 2 Mode With -3.5 Db De-Emphasis
IDT SerDes Notes Settings of Relevant Fields in the Transmit Levels S[x]TXLCTL0 & S[x]TXLCTL1 Registers Drive De-empha- De-empha- Level sized Drive TDVL_FS3DBG1 CDC_FS3DBG1 FDC_FS3DBG1 TX_SLEW_G1 sis (dB) (mV) Level (mV) -3.4 -3.4 -3.3 -3.4 -3.5 -3.6 -3.7 -3.6 -3.6 -3.6 -3.6 -3.8 -4.0...
Page 152 IDT SerDes Notes Settings of Relevant Fields in the Transmit Levels S[x]TXLCTL0 & S[x]TXLCTL1 Registers De-empha- Drive De-empha- sized Drive Level TDVL_FS3DBG2 CDC_FS3DBG2 FDC_FS3DBG2 TX_SLEW_G2 sis (dB) Level (mV) (mV) -3.1 0x15 -3.0 0x14 -3.0 0x13 -3.0 0x12 -3.0 0x11 -3.1 0x10 -3.1...
Page 153: Table 8.7 Serdes Transmit Driver Settings In Gen 2 Mode With -6.0 Db De-Emphasis
IDT SerDes Notes Settings of Relevant Fields in the Transmit Levels S[x]TXLCTL0 & S[x]TXLCTL1 Registers De-empha- Drive De-empha- sized Drive Level TDVL_FS6DBG2 CDC_FS6DBG2 FDC_FS6DBG2 TX_SLEW_G2 sis (dB) Level (mV) (mV) 0x19 -6.3 -6.4 0x18 -6.3 0x17 -6.1 0x16 -6.0 0x15 -5.9 0x14 -5.9...
Page 154: Figure 8.1 Relationship Between Coarse And Fine De-Emphasis Controls
IDT SerDes Notes In addition to the SerDes settings described above, the user may apply an amplitude boost to the drive swing by setting the TX_AMPBOOST field in the S[x]TXLCTL0 register. Amplitude boost may be applied on a per-lane basis. Amplitude boost may be applied to increase the drive swings above the values shown in Tables 8.5, 8.6, and 8.7.
Page 155: Transmit Margining Using The Pci Express Link Control 2 Register
IDT SerDes Notes The fine de-emphasis registers allow modification of the de-emphasis in fine steps. There is a fine de- emphasis control per PHY operating mode. – When the PHY operates in Gen 1 data rate with -3.5 dB de-emphasis, the fine de-emphasis is controlled by the FDC_FS3DBG1 field in the S[x]TXLCTL0 register.
Page 156: Low-Swing Transmitter Voltage Mode
IDT SerDes Notes Full Swing Low Swing Mode Mode (mV) (mV) Table 8.8 PCI Express Transmit Margining Levels Supported by the PES12NT12G2 Note that in compliance mode (i.e., when the associated port’s PHY LTSSM is in the Polling.Compliance state), the SerDes transmit level is controlled by the TM field in the associated port’s PCIELCTL2 register, and the de-emphasis setting is controlled by the LTSSM based on the rules described in Section 4.2.6.2.2 of the PCI Express Base Specification.
Page 157: Table 8.9 Serdes Transmit Drive Swing In Low Swing Mode At Gen 1 Speed
IDT SerDes Notes Drive Level TDVL_LSG1 (mV) 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 Table 8.9 SerDes Transmit Drive Swing in Low Swing Mode at Gen 1 speed Drive Level TDVL_LSG2 (mV) 0x0F 0x0E...
Page 158: Receiver Equalization Controls
IDT SerDes Notes Drive Level TDVL_LSG2 (mV) 0x02 0x01 0x00 Table 8.10 SerDes Transmit Drive Swing in Low Swing Mode at Gen 2 Speed (Part 2 of 2) When the PHY enters the Polling.Compliance state and low-swing mode is enabled, the following occurs: –...
Page 159 IDT SerDes Notes It is possible to explicitly power-down a SerDes quad by setting the POWERDN bit in the corresponding SerDes Control (S[x]CTL) register. Refer to the definition of this field for further details. Powering-down a SerDes shared by multiple ports results in all such ports being affected. Refer to section SerDes Numbering and Port Association on page 8-1 for a list of port/SerDes associations.
Page 160 IDT SerDes Notes PES12NT12G2 User Manual 8 - 16 July 10, 2013...
Page 161: Power Management
Chapter 9 Power Management ® Overview Notes This chapter describes the PES12NT12G2 device power management support. This chapter does not describe link active state power management (ASPM). For a description of this topic, refer to section Link Active State Power Management (ASPM) on page 7-12. Located in the configuration space of each function in the PES12NT12G2 (i.e., PCI-to-PCI Bridge, NT, and DMA functions) is a power management capability structure.
Page 162: Table 9.1 Pes12Nt12G2 Power Management State Transition Diagram
IDT Power Management Notes Partition Reset Uninitialized Active cold Figure 9.1 PES12NT12G2 Power Management State Transition Diagram From State To State Description D0 Uninitialized Partition reset (any type). D0 Uninitialized D0 Active Function configured by software D0 Active The Power Management State (PMSTATE) field in the PCI Power Management Control and Status (PMCSR) register is written with the value that corresponds to the D3 state.
Page 163 IDT Power Management Notes – Any error message resulting from the reception of a TLP is reported in the same manner as when the bridge is not in D3 (e.g, generation of an ERR_NONFATAL message to the root). • This requires transitioning the link to the L0 state when error reporting is enabled and the link is not in L0.
Page 164: Power Management Event (Pme) Messages
IDT Power Management Notes • This requires transitioning the link to the L0 state when error reporting is enabled and the link is not in L0. – Error messages resulting from any event other than the receipt of a TLP are discarded (i.e., no error message is generated).
Page 165: Nt Function Mode Or Nt With Dma Function Mode
IDT Power Management Notes – When PME_TO_Ack aggregation is abandoned, the PES12NT12G2 makes no attempt to abandon the PME_Turn_Off and PME_TO_Ack protocol on downstream switch ports. Devices downstream of the switch are allowed to respond with a PME_TO_Ack and transition to L2/L3 Ready.
Page 166 IDT Power Management Notes PES12NT12G2 User Manual 9 - 6 July 10, 2013...
Page 167: Notes
Chapter 10 Transparent Switch Operation ® Overview Notes As noted in Chapter 1, each PES12NT12G2 switch partition operates logically as a completely indepen- dent PCI Express switch that implements the behavior and capabilities required of a switch by the PCI Express Base Specification Revision 2.1.
Page 168: Virtual Channel Support
IDT Transparent Switch Operation Virtual Channel Support Notes In section Virtual Channel Support on page 4-5 there is a description of virtual channel support in the PES12NT12G2 ports. The PCI-to-PCI bridge function contains a VC Capability Structure that provides architected port arbitration and TC/VC mapping for VC0. For port operating modes in which the PCI-to-PCI bridge function is function 0 of the port, the VC Capability Structure in this function provides architected port arbitration and TC/VC mapping for all functions of the port.
Page 169 IDT Transparent Switch Operation Notes When a CplDLk is received by the locked downstream switch port, it forwards the CplDLk transaction to the upstream port and locks the upstream port so that all subsequent TLPs destined to the locked port from other ports (except the locked downstream switch port) are blocked until the lock is released.
Page 170: Interrupts
IDT Transparent Switch Operation Interrupts Notes The switch’s PCI-to-PCI bridge functions may be configured to issue interrupts due to several condi- tions. The interrupt sources each have a corresponding status bit in the PCI-to-PCI bridge function’s Inter- rupt Status (P2PINTSTS) register. –...
Page 171: Legacy Interrupt Aggregation
IDT Transparent Switch Operation Notes When a port is configured to generate INTx messages, only INTA is used. Note that the Interrupt Pin register (INTRPIN) must be programmed accordingly. The MSI capability structure associated with the upstream port’s PCI-to-PCI bridge function is not by default part of the PCI capability structure linked-list located in the function’s configuration space.
Page 172: Access Control Services
IDT Transparent Switch Operation Notes An Assert_INTx message is sent to the root by the upstream port when the aggregated state of the corresponding interrupt in the upstream port transitions from a negated to an asserted state. A Deassert_INTx message is sent to the root by the upstream port when the aggregated state of the corre- sponding interrupt in the upstream port function transitions from an asserted to a negated state.
Page 173: Figure 10.2 Acs Source Validation Example
IDT Transparent Switch Operation Notes – ACS Peer-to-Peer Completion Redirect – ACS Upstream Forwarding – ACS Peer-to-Peer Egress Control – ACS Direct Translated Peer-to-Peer When a port operates in one of the multi-function upstream port modes listed above, the PCI-to-PCI bridge function supports the following ACS operations –...
Page 174: Figure 10.3 Acs Peer-To-Peer Request Re-Direct At A Downstream Switch Port
IDT Transparent Switch Operation Notes Upstream Port Intended TLP Route ACS Re-directed Route Bridge Virtual PCI Bus ACS Peer-to- Peer Request Re-direct Bridge Bridge Downstream Ports Figure 10.3 ACS Peer-to-Peer Request Re-direct at a Downstream Switch Port Figure 10.4 shows an example of ACS upstream forwarding at a downstream switch port. As with ACS Peer-to-Peer forwarding, the offending TLP received by the downstream switch port is re-directed towards the root-complex.
Page 175: Table 10.4 Prioritization Of Acs Checks For Request Tlps
IDT Transparent Switch Operation Notes Upstream Upstream Port Port ACS Peer-to- Peer Request Redirect Intended TLP Route ACS Re-directed Route Bridge Endpoint Endpoint Bridge Non Transparent Interconnect Partition 1 – Virtual PCI Bus Partition 2 – Virtual PCI Bus Bridge Bridge Bridge Bridge...
Page 176: Ecrc Support
IDT Transparent Switch Operation Notes ACS Check Priority Comment ACS Upstream For- 2 (Highest) Applicable to request or completion TLPs warding received by the downstream switch port on its ingress link that target the port’s egress link. This is not considered a peer-to-peer transfer. ACS Peer-to-Peer 1 (Lowest) Applicable to non-relaxed-ordered peer-to-peer...
Page 177: Error Detection And Handling By The Pci-To-Pci Bridge Function
IDT Transparent Switch Operation Error Detection and Handling by the PCI-to-PCI Bridge Notes Function This section describes error conditions detected by the PCI-to-PCI bridge function. This includes phys- ical, data-link, and transaction layer errors detected by the port, as well as routing errors associated with the PCI-to-PCI bridge function in the port.
Page 178: Data Link Layer Errors
IDT Transparent Switch Operation Notes PCI Express Function- Base Error Condition Specific Action Taken Specification Error Section Link Errors (8b/10b, loss of symbol 4.2.4.6 Correctable error process- lock, elastic buffer overflow/underflow, lane-to-lane deskew) Any TLP or DLLP framing rule violation. 4.2.2 Correctable error process- Table 10.7 Physical Layer Errors...
Page 179: Transaction Layer Errors
IDT Transparent Switch Operation Transaction Layer Errors Notes Table 10.9 lists non-ACS error checks associated with a PCI-to-PCI bridge function and the action taken when an error is detected. ACS error checks and handling are discussed in section ACS Error Handling on page 10-18.
Page 180: Table 10.9 Transaction Layer Errors Associated With The Pci-To-Pci Bridge Function
IDT Transparent Switch Operation Notes Role Express Based Function Error Base (Advisory) Specific Action Taken Condition Specifica- Error Error tion Reporting Section Condition Poisoned TLP 2.7.2.2 Advisory when Detected Parity Error (DPE) bit in the received the correspond- PCISTS or SECSTS register set ing error is con- appropriately.
Page 181 IDT Transparent Switch Operation Notes Role Express Based Function Error Base (Advisory) Specific Action Taken Condition Specifica- Error Error tion Reporting Section Condition Unexpected comple- 2.3.2 Yes if a func- Advisory when Non-advisory case: uncorrectable tion received tion claims the correspond- error processing.
Page 182: Table 10.11 Conditions Handled As Unexpected Completions (Uc) By The Pci-To-Pci Bridge
IDT Transparent Switch Operation Notes PCI Express Base Conditions Handled as UR Description Specification Section Poisoned IO request, memory write Reception of a poisoned IO request, memory 2.7.2.2 request, type 0 configuration write write request, type 0 configuration write request, or message with data targeting request, or message with data (except Vendor the bridge function Defined messages) that targets a switch port’s...
Page 183: Table 10.12 Ingress Tlp Formation Checks Associated With The Pci-To-Pci Bridge Function
IDT Transparent Switch Operation Notes TLP Type Error Check TLP must have a valid FMT/TYPE combination Data payload length <= Max_Payload_Size (i.e., MPS field in PCIEDCTL register) All TLPs with data LENGTH field must match actual payload data (i.e., FMT[1]=1) All TLPs with ECRC Actual TLP length must match calculated length (i.e., TD=1)
Page 184: Table 10.13 Egress Malformed Tlp Error Checks
IDT Transparent Switch Operation Notes TLP Type Error Check TLP traffic class (TC) must be mapped to VC0. TC to VC mapping is controlled by the TC/VC Map (TCVCMAP) field in the egress port’s VC Resource 0 Control (VCR0CTL) register of the PCI-to-PCI bridge function.
Page 185: Table 10.14 Acs Violations For Ports Operating In Downstream Switch Port Mode
IDT Transparent Switch Operation Notes Role Based PCI Express (Advisory) Base ACS Check Error Action Taken Specification Reporting Section Condition ACS Source Validation 6.12.1.1 Advisory when If TLP is a non-posted request, a completion the correspond- with ‘completer abort’ status is generated. ing error is con- Note that this is not considered a completer figured as non-...
Page 186: Table 10.15 Prioritization Of Transaction Layer Errors
IDT Transparent Switch Operation Notes Transaction Layer Error Pollution Per section 6.2.3.2.3 of PCI Express Base Specification 2.1, transaction layer errors may be prioritized to prevent error pollution in AER. Error pollution rules only apply to errors associated with the reception of a TLP.
Page 187: Table 1.1 Table
IDT Transparent Switch Operation Notes TLP Received by Done Function Handle per Table 13.9 Receiver Overflow Error? Handle per Table 13.9 ECRC TLP Dropped? Error? If ECRC error detected, handle per Table 13.9 but do not log Malformed error; Else, Malformed TLP? handle per Table 13.9 If ECRC detected, handle per Table 13.14...
Page 188 IDT Transparent Switch Operation Notes Note the following: – Except for ECRC and Poisoned TLP errors, all other errors detected on the received TLP cause the detecting function to consume, drop, or nullify the TLP. – Receiver overflow errors are always checked and logged. –...
Page 189: Routing Errors
IDT Transparent Switch Operation Routing Errors Notes This section lists TLP routing errors that are detected by the PCI-to-PCI bridge function in the PES12NT12G2 ports. Except for completions (section Completions (Routed by ID) on page 10-24), all of these errors are treated as unsupported requests. Address Routed TLPs –...
Page 190: Error Emulation Control In The Pci-To-Pci Bridge Function
IDT Transparent Switch Operation Notes Completions (Routed by ID) Completions for which there is no valid route across the switch (i.e., the completion can’t be forwarded) are treated as unexpected completions. This includes the following cases: – Completions that attempt to route back onto the link on which they were received, if ACS Upstream Forwarding is disabled.
Page 191 IDT Transparent Switch Operation Notes • The severity of the error must be set to fatal in the AERUESV register. – To emulate the detection of an advisory uncorrectable non-fatal error: – The desired error bit must be set in the P2PUEEM register. The error bit selected must qualify for advisory handling as specified in the PCI Express 2.1 specification.
Page 192 IDT Transparent Switch Operation Notes PES12NT12G2 User Manual 10 - 26 July 10, 2013...
Page 193: Hot-Plug And Hot-Swap
Chapter 11 Hot-Plug and Hot-Swap ® Overview Notes As illustrated in Figures 11.1 through 11.3, a PCI Express switch may be used in one of three hot-plug configurations. Figure 11.1 illustrates the use of the PES12NT12G2 switch in an application in which two downstream switch ports are connected to slots into which add-in cards may be hot-plugged.
Page 194: Figure 11.2 Hot-Plug With Switch On Add-In Card Application
IDT Hot-Plug and Hot-Swap Notes Upstream Link Add-In Card Port 0 PES12NT12G2 Port x Port y PCI Express PCI Express Device Device Figure 11.2 Hot-Plug with Switch on Add-In Card Application Upstream Link Carrier Card Port 0 PES12NT12G2 Master SMBus Port x Port y SMBus I/O...
Page 195: Hot-Plug Signals
IDT Hot-Plug and Hot-Swap Notes Associated with all PES12NT12G2 ports is a hot-plug controller. However, hot-plug is only supported when a port is configured to operate in downstream switch port mode. In all other port operating modes, hot-plug is not supported and the hot-plug signals associated with the port are placed in a negated state. Refer to Chapter 5 for details on port operating modes.
Page 196: Table 11.2 Negated Value Of Unused Hot-Plug Output Signals
IDT Hot-Plug and Hot-Swap Notes Negated Output Negated Output Value with Non- Value with Signal Inverted Polarity Inverted Polarity (IPXxxx = 0) (IPXxxx = 1) PxAIN 1 (high) 0 (low) PxILOCKP 0 (low) 1 (high) PxPEP 0 (low) 1 (high) PxPIN 1 (high) 0 (low)
Page 197: Port Reset Outputs
IDT Hot-Plug and Hot-Swap Notes The default value of fields in the PCIESCTL register following any reset other than a switch fundamental reset (e.g., a partition fundamental reset, partition hot reset, partition upstream secondary bus, or partition downstream secondary bus reset) is determined by the value of the corresponding field in the port’s PCI Express Slot Control Initial Value (PCIESCTLIV) register when the corresponding hot-plug capability is enabled.
Page 198: Power Good Controlled Reset Output
IDT Hot-Plug and Hot-Swap Notes PWR2RST RST2PWR PxPEP PxRSTN Figure 11.4 Power Enable Controlled Reset Output Mode Operation While slot power is disabled, the corresponding downstream switch port reset output is asserted. When slot power is enabled by writing a zero to the PCC bit, the Port x Power Enable Output (PxPEP) is asserted and then power to the slot is enabled and the corresponding downstream switch port reset output is negated.
Page 199: Hot-Plug Events
IDT Hot-Plug and Hot-Swap Notes possible to meet a profile’s power level invalid to reset asserted timing specification (i.e., PxPWRGDN to PxRSTN). Systems that require a shorter time interval may implement this functionality external to the switch. Hot-Plug Events The hot-plug controller associated with a downstream switch port slot may generate an interrupt or wakeup event.
Page 200: Hot-Swap
IDT Hot-Plug and Hot-Swap Notes GPEN is a GPIO alternate function. The GPIO pin will not be asserted when GPEN is asserted unless it is configured to operate as an alternate function. Whenever a port signals a hot-plug event through asser- tion of the GPEN signal, the corresponding port’s status bit is set in the General Purpose Event Status (GPESTS) register.
Page 201: Smbus Interfaces
Chapter 12 SMBus Interfaces ® Overview Notes The PES12NT12G2 has two SMBus interfaces. The slave SMBus interface provides full access to all software-visible registers, allowing every register in the device to be read or written by an external SMBus master. The slave SMBus may also be used to program the serial EEPROM used for initialization. The Master SMBus interface provides connection for an optional external serial EEPROM used for initialization and optional external I/O expanders.
Page 202: Serial Eeprom
IDT SMBus Interfaces Notes The goal of the reset procedure is to ensure interoperability with serial EEPROM or IO expander devices that do not have a reset signal input. When the switch is reading from these devices and a fundamental reset is applied to the switch (e.g., via assertion of the PERSTN input signal), the I C bus may be left in an unpredictable state that prevents the switch’s master SMBus interface from creating a START condition on...
Page 203: Initialization From Serial Eeprom
IDT SMBus Interfaces Initialization from Serial EEPROM Notes During initialization from the optional serial EEPROM, the master SMBus interface reads configuration blocks from the serial EEPROM and updates corresponding registers in the switch. Any software-visible register in the device may be initialized with values stored in the serial EEPROM. All software-visible regis- ters have a system address in the PES12NT12G2’s global address space.
Page 204: Figure 12.2 Single Double-Word Initialization Sequence Format
IDT SMBus Interfaces Notes There are five configuration block types that may be stored in the serial EEPROM. – Single double-word initialization sequence – Sequential double-word initialization sequence – Jump block – Wait block – Configuration done sequence The first type is a single double-word initialization sequence. A single double-word initialization sequence occupies seven bytes in the serial EEPROM and is used to initialize a single double-word register quantity.
Page 205: Figure 12.3 Sequential Double-Word Initialization Sequence Format
IDT SMBus Interfaces Notes CFG TYPE Reserved Byte 0 (must be zero) Byte 1 SYSADDR[9:2] Byte 2 SYSADDR[17:10] Byte 3 NUMDW[7:0] Byte 4 NUMDW[15:8] Byte 5 DATA0[7:0] Byte 6 DATA0[15:8] Byte 7 DATA0[23:16] Byte 8 DATA0[31:24] Byte 4n+5 DATAn[7:0] Byte 4n+ 6 DATAn[15:8] Byte 4n+7 DATAn[23:16]...
Page 206: Figure 12.5 Execution Of A Jump Configuration Block
IDT SMBus Interfaces Notes During serial EEPROM initialization, when the SMBus master interface reads a jump configuration block, it evaluates the switch mode to decide if the jump should be taken as shown in pseudo code in Figure 12.5. When the jump is not taken, sequential execution of the Serial EEPROM initialization continues at the address immediately following the jump configuration block.
Page 207: Figure 12.6 Example Of Multiple Configuration Images In Serial Eeprom
IDT SMBus Interfaces Notes Serial EEPROM Jump 0 Block Jump 1 Block Configuration Image A Configuration Done Block Configuration Image B Configuration Done Block Configuration Image C Configuration Done Block 0xFFFF Figure 12.6 Example of Multiple Configuration Images in Serial EEPROM The PES12NT12G2 imposes no limitations on the number of jump configuration blocks that may be executed while reading the serial EEPROM.
Page 208: Figure 12.7 Wait Configuration Block
IDT SMBus Interfaces Notes CFG TYPE Reserved Byte 0 (must be zero) Byte 1 SYSADDR[9:2] Byte 2 SYSADDR[17:10] Byte 3 DATA[7:0] Byte 4 DATA[15:8] Byte 5 DATA[23:16] Byte 6 DATA[31:24] Byte 7 MASK[7:0] Byte 8 MASK[15:8] Byte 9 MASK[23:16] Byte 10 MASK[31:24] Figure 12.7 Wait Configuration Block When configuring the PES12NT12G2 device via EEPROM, the Wait configuration block can be used to...
Page 209: Figure 12.8 Configuration Done Sequence Format
IDT SMBus Interfaces Notes CFG TYPE Reserved Byte 0 (must be zero) Byte 1 CHECKSUM[7:0] Figure 12.8 Configuration Done Sequence Format The checksum in the configuration done sequence enables the integrity of the serial EEPROM initializa- tion to be verified. The checksum is computed in the following manner. An 8-bit counter is initialized to zero and the 8-bit sum is computed over the configuration bytes stored in the serial EEPROM, including the entire contents of the configuration done sequence, with the checksum field initialized to zero.
Page 210: Programming The Serial Eeprom
IDT SMBus Interfaces Notes Error Action Taken Configuration Done Sequence checksum - Set RSTHALT bit in SWCTL register mismatch with that computed - ICSERR bit is set in the SMBUSSTS register - EED bit is set in the SMBUSSTS register - Abort initialization, set EEPROMDONE bit in the SMBUSSTS register Invalid configuration block type...
Page 211: I/O Expanders
IDT SMBus Interfaces Notes To write a byte to the serial EEPROM, the root should configure the ADDR field with the byte address of the serial EEPROM location to be written and set the OP field to “write.” If the serial EEPROM is not busy (i.e., the BUSY bit is cleared), then the write operation may be initiated by writing the value to be written to the DATA field.
Page 212 IDT SMBus Interfaces Notes SMBus I/O Section Functionality Expander Lower Unused Upper Unused Lower Port 17 hot-plug Upper Port 19 hot-plug Lower Unused Upper Unused Lower / Upper Hot-plug MRL inputs (Ports 0 through 3, 8, 10, 16, 18) Lower / Upper Hot-plug MRL inputs (Ports 9, 11, 17, 19) Lower / Upper Hot-plug electromechanical interlock (Ports 0, 2, 8,...
Page 213 IDT SMBus Interfaces Notes The following I/O expander configuration sequence is issued by the switch to I/O expanders 0 through 11, 14, 15, and 16 (i.e., the ones that contain general port hot-plug signals and electromechanical interlock signals). The I/O expander registers in the sequence are located in the I/O expander device. Step 1.
Page 214 IDT SMBus Interfaces Notes The following I/O expander configuration sequence is issued by the switch to I/O expanders 20 and 21 (i.e., the one that contains port reset outputs). Step 1. Write the reset status for all ports to the lower eight I/O expander pins (i.e., I/O-0.0 through I/O- 0.7) to I/O expander register 2.
Page 215 IDT SMBus Interfaces Notes System design recommendations: – I/O expander addresses and default output values may be configured during serial EEPROM initialization. If I/O expander addresses are configured via the serial EEPROM, then the switch will initialize the I/O expanders when normal device operation begins following the completion of the fundamental reset sequence.
Page 216: Table 12.6 I/O Expander 0 Through 11 Port Mapping
IDT SMBus Interfaces Notes I/O Expander Associated Ports Port 0 Ports 8 and 16 Port 2 Unused Ports 1 and 3 Unused Port 10 Port 18 Ports 9 and 11 Unused Ports 17 and 19 Unused Table 12.6 I/O Expander 0 through 11 Port Mapping I/O Expander 12 SMBus I/O Expander...
Page 217 IDT SMBus Interfaces Notes I/O Expander 13 SMBus I/O Expander Type Signal Description 0 (I/O-0.0) P9MRLN Port 9 manually operated retention latch (MRL) input 1 (I/O-0.1) P11MRLN Port 11 manually operated retention latch (MRL) input 2 (I/O-0.2) Unused 3 (I/O-0.3) Unused 4 (I/O-0.4) P17MRLN...
Page 218: Table 12.11 Pin Mapping I/O Expander 16
IDT SMBus Interfaces Notes I/O Expander 15 SMBus I/O Expander Type Signal Description 0 (I/O-0.0) P1ILOCKST Port 1 electromechanical interlock state input 1 (I/O-0.1) P3ILOCKST Port 3 electromechanical interlock state input 2 (I/O-0.2) Unused 3 (I/O-0.3) Unused 4 (I/O-0.4) P10ILOCKST Port 10 electromechanical interlock state input 5 (I/O-0.5) Unused...
Page 219 IDT SMBus Interfaces Notes SMBus I/O Expander Type Signal Description 11 (I/O-1.3) Unused 12 (I/O-1.4) P17ILOCKP Port 17 electromechanical interlock output 13 (I/O-1.5) P19ILOCKP Port 19 electromechanical interlock output 14 (I/O-1.6) Unused 15 (I/O-1.7) Unused Table 12.11 Pin Mapping I/O Expander 16 (Part 2 of 2) I/O-x.y corresponds to the notation used for PCA9555 port x I/O pin y.
Page 220: Table 12.14 Pin Mapping Of I/O Expander 19
IDT SMBus Interfaces Notes I/O Expander 18 SMBus I/O Expander Type Signal Description 0 (I/O-0.0) P0ACTIVEN Port 0 Link active status output 1 (I/O-0.1) P1ACTIVEN Port 1 Link active status output 2 (I/O-0.2) P2ACTIVEN Port 2 Link active status output 3 (I/O-0.3) P3ACTIVEN Port 3 Link active status output...
Page 221 IDT SMBus Interfaces Notes SMBus I/O Expander Type Signal Description 11 (I/O-1.3) P19ACTIVEN Port 19 Link active status output 12 (I/O-1.4) Unused 13 (I/O-1.5) Unused 14 (I/O-1.6) Unused 15 (I/O-1.7) Unused Table 12.14 Pin Mapping of I/O Expander 19 (Part 2 of 2) I/O-x.y corresponds to the notation used for PCA9555 port x I/O pin y.
Page 222: Slave Smbus Interface
IDT SMBus Interfaces Notes I/O Expander 21 IO Expanders 21 provides a copy of the port reset outputs driven via the hot-plug IO expanders (i.e., IO expanders 0 through 11). Therefore, this IO expander allows the use of the port reset outputs without needing to enable hot-plug on the port(s).
Page 223: Smbus Transactions
IDT SMBus Interfaces Notes Address Address Bit Value SSMBADDR[1] SSMBADDR[2] Table 12.17 Slave SMBus Address SMBus Transactions The slave SMBus interface responds to the following SMBus transactions initiated by an SMBus master. See the SMBus Specification Version 2.0, August 3, 2000, SBS Implementers Forum for a detailed descrip- tion of these transactions.
Page 224: Table 12.19 Csr Register Read Or Write Operation Byte Sequence
IDT SMBus Interfaces Notes Name Description Field FUNCTION This field encodes the type of SMBus operation. 0 - CSR register read or write operation 1 - Serial EEPROM read or write operation 2 through 7 - Reserved SIZE This field encodes the data size of the SMBus transaction. 0 - Byte 1 - Word 2 - Block...
Page 225: Table 12.20 Csr Register Read Or Write Cmd Field Description
IDT SMBus Interfaces Notes Byte Field Description Position Name DATALM Data Lower Middle. Bits [15:8] of data doubleword. DATAUM Data Upper Middle. Bits [23:16] of data doubleword. DATAUU Data Upper. Bits [31:24] of data doubleword. Table 12.19 CSR Register Read or Write Operation Byte Sequence (Part 2 of 2) Refer to section Overview on page 12-1 for details on PES12NT12G2’s system addresses and the Global Address Space.
Page 226: Table 12.21 Serial Eeprom Read Or Write Operation Byte Sequence
IDT SMBus Interfaces Notes The RERR and WERR bits are driven by the switch as status bits that indicate whether or not the switch’s SMBus slave in- terface accepted the register read/write command (the switch accepts the access if it has the correct byte sequence). When a byte sequence refers to a register offset that is not listed or is regarded as a reserve register, the RERR and WERR bits will be set after a read or write operation is performed.
Page 227: Table 12.22 Serial Eeprom Read Or Write Cmd Field Description
IDT SMBus Interfaces Notes Name Type Description Field Serial EEPROM Operation. This field encodes the serial EEPROM operation to be performed. 0 - Serial EEPROM write 1 - Serial EEPROM read Use Specified Address. When this bit is set the serial EEPROM SMBus address specified in the EEADDR byte is used instead of that specified in the MSMBADDR field in the SMBUSSTS register.
Page 228: Figure 12.13 Serial Eeprom Read Using Smbus Block Write/Read Transactions With Pec
IDT SMBus Interfaces Notes Switch Slave CCODE BYTCNT=4 CMD=read EEADDR ADDRL SMBus Address START,END ADDRU Switch Slave CCODE (Switch not ready with data) SMBus Address START,END Switch Slave CCODE Switch Slave BYTCNT=5 CMD (status) EEADDR SMBus Address START,END SMBus Address ADDRL ADDRU DATA...
Page 229: Setting Up I2C Commands For Block Transactions
IDT SMBus Interfaces Notes Switch Slave CCODE CMD=read ADDRL SMBus Address START, Word Switch Slave CCODE ADDRU SMBus Address END, Byte Switch Slave CCODE (Switch not ready with data) SMBus Address START,Word Switch Slave CCODE SMBus Address START,Word Switch Slave CMD (status) ADDRL SMBus Address...
Page 230: Smbus Transactions
IDT SMBus Interfaces Notes Byte Field Description Position Name CCODE Command Code. Slave Command Code field BYTECNT Byte Count. The byte count field is only transmitted for block type SMBus transactions. SMBus word and byte accesses do not contain this field. The byte count field indicates the number of bytes following the byte count field when performing a write or setting up for a read.
Page 231: Table 12.24 Slave Smbus Command Code Fields
IDT SMBus Interfaces Notes Field Description Fields Name End of transaction indicator. Setting both START and END signifies a single transaction sequence 0 - Current transaction is not the last read or write sequence. 1 - Current transaction is the last read or write sequence. START Start of transaction indicator.
Page 232: Examples Of Setting Up The I2C Csr Byte Sequence For A Csr Register Read
IDT SMBus Interfaces Notes Field Type Description Field Name Reserved. Must be zero RERR Read-Only Read Error. This bit is set if the last CSR read SMBus transaction and Clear was not claimed by a device. Success indicates that the transaction was claimed and not that the operation completed without error.
Page 233: Table 12.27 I2C Command Byte Array Indices
IDT SMBus Interfaces Notes The CSR_Offset is shifted 2 bits to the right so that DWORD aligned register offsets are only accessible; this step may not be needed for some devices. Read BYTE Setup Steps 2 and 3 show how each index in the CSR byte sequence array is set for a BYTE read operation. For step 3, the transaction size is a value that is passed to the I2C control function so that it knows how many bytes are being dealt with in the CSR byte sequence.
Page 234: Table 12.28 I2C Command Byte Array Indices
IDT SMBus Interfaces Notes Read WORD Setup Steps 2 and 3 in this section (see Step 1 above) shows how each index in the CSR byte sequence array is set for a WORD read operation. For step 3, the transaction size is a value that is passed to the I2C control function so that it knows how many bytes are being dealt with in the CSR byte sequence.
Page 235: Examples Of Setting Up The I2C Csr Byte Sequence For A Csr Register Write
IDT SMBus Interfaces Notes Step 2. Prepare the I2C byte array Table 12.29 shows the block byte array assignments (in increasing index order starting from index 0). Address offset 0 is used in the examples. Index # Assignment Description CCode_i |= CCode_Block BKCnt_i = TranSize_BkWtHeader BKCmd_i = CMD_Init | CMD_DWORD | CMD_OPRD BKOfL_i = CSR_Offset &...
Page 236: Table 12.30 I2C Command Byte Array Indices
IDT SMBus Interfaces Notes Write BYTE Setup Steps 2 and 3 show how each index in the CSR byte sequence array is set for a BYTE write operation. Step 2. Prepare the I2C byte array Table 12.30 shows the block byte array assignments (in increasing index order starting from index 0). Address offset 0 is used in the examples.
Page 237: Table 12.31 I2C Command Byte Array Indices
IDT SMBus Interfaces Notes Write WORD Setup Steps 2 and 3 shows how each index in the CSR byte sequence array is set for a WORD write opera- tion. Step 2. Prepare the I2C byte array Table 12.31 shows the block byte array assignments (in increasing index order starting from index 0). Address offset 0 is used in the examples.
Page 238: Table 12.32 I2C Command Byte Array Indice
IDT SMBus Interfaces Notes Index 6 - Set the upper data byte BKDtL_i+1 = high byte of word data BKDtL_i+1 = 0x22 (of 0xBBAA2211) Step 3. Calculate the transaction size TranSize TranSize_Block + word_length 5 + 2 Write DWORD Setup Steps 2 and 3 show how each index in the CSR byte sequence array is set for a DWORD write opera- tion.
Page 239 IDT SMBus Interfaces Notes Index 3 - Set the lower CSR register offset BKOfL_i = CSR_Offset & 0xFF BKOfL_i = 0x00 & 0xFF = 0 Index 4 - Set the upper CSR register offset BKOfU_i = (CSR_Offset & 0xFF00) >> 8 BKOfU_i = (0x00 &...
Page 240 IDT SMBus Interfaces Notes PES12NT12G2 User Manual 12 - 40 July 10, 2013...
Page 241: General Purpose I/O
Chapter 13 General Purpose I/O ® Overview Notes The switch has 9 General Purpose I/O (GPIO) pins that may be individually configured as general purpose inputs, general purpose outputs, or alternate functions. GPIO pins are controlled by the General Purpose I/O Function (GPIOFUNC), General Purpose I/O Configuration (GPIOCFG), General Purpose I/O Data (GPIOD), and General Purpose I/O Alternate Function Select (GPIOAFSEL) register.
Page 242: Table 13.2 Gpio Alternate Function Pin Assignment
IDT General Purpose I/O Notes GPIO Alternate Alternate Function 0 Function 1 PART0PERSTN P16LINKUPN PART1PERSTN P16ACTIVEN PART2PERSTN P4LINKUPN PART3PERSTN P4ACTIVEN FAILOVER0 P0LINKUPN GPEN P0ACTIVEN FAILOVER1 FAILOVER3 FAILOVER2 P8LINKUPN IOEXPINTN P8ACTIVEN Table 13.2 GPIO Alternate Function Pin Assignment Alternate function signals are described in Table 13.3. Signal Type Name/Description...
Page 243: Notes
Chapter 14 Non-Transparent Switch Operation ® Overview Notes The term non-transparent operation is used in this document to describe the operation of the NT func- tion. This chapter describes the PES12NT12G2’s non-transparent operation. The PCI Express architectural model is one in which a root, typically the main CPU, is responsible for configuring a tree of endpoints (i.e., a hierarchy of virtual PCI buses).
Page 244: Bar Limit
IDT Non-Transparent Switch Operation Notes Description BAR 0 32-bit BAR that maps 4 KB NT-endpoint configuration registers Lower half of 64-bit BAR that maps 4 KB NT-endpoint configuration registers 32-bit BAR with direct address translation Lower half of 64-bit BAR with direct address translation BAR 1 Upper half of 64-bit BAR that maps 4 KB NT-endpoint configuration registers 32-bit BAR with direct address translation...
Page 245: Figure 14.1 Bar Limit Operation
IDT Non-Transparent Switch Operation Notes Associated with each BAR is a BAR Limit Address (BARLIMITx) register. The limit address specified by this register allows arbitrary control of the aperture size associated with a BAR. Using this capability, the effective aperture size may be set arbitrarily to any value, in 1 KB multiples, up to the power of two aperture size requested by the BAR.
Page 246: Mapping Nt Configuration Space To Bar 0
IDT Non-Transparent Switch Operation Mapping NT Configuration Space to BAR 0 Notes As mentioned above, the 4 KB configuration space associated with the NT endpoint may be mapped into 32-bit memory using BAR 0. BAR 0 and BAR 1 may be paired to map the 4 KB configuration space associated with the NT endpoint into 64-bit memory.
Page 247: Lookup Table Address Translation
IDT Non-Transparent Switch Operation Notes The destination partition of the translated TLP is specified by the Translated Partition (TPART) field in the corresponding BARSETUPx register. If the destination partition associated with the translated TLP is invalid (e.g., there is no NT endpoint associated with the destination partition, the destination partition is not in the active state, or the destination partition is the same as the partition on which the TLP was received), then the TLP is treated as an unsupported request by the NT endpoint that received the request.
Page 248: Figure 14.4 Lookup Table Entry Format
IDT Non-Transparent Switch Operation Notes When the BAR is configured to operate as an address window with lookup table address translation, valid values for the SIZE field in the corresponding BARSETUPx register are 14 through 37 (values greater than 16 require a 64-bit BAR). Setting the SIZE field outside this range produces undefined results. Associated with a BAR configured to use lookup table address translation is a 12 or 24-entry lookup table.
Page 249: Table 14.2 12-Entry Lookup Table Parameters
IDT Non-Transparent Switch Operation Notes The destination partition associated with the translated TLP is specified by the partition field in the lookup table entry. If the partition associated with the translated TLP is invalid (e.g., there is no NT endpoint associated with the destination partition, the destination partition is not in the active state, or the destination partition is the same as the original partition), then the TLP is treated as an unsupported request by the NT endpoint that received the request.
Page 250: Table 14.3 24-Entry Lookup Table Parameters
IDT Non-Transparent Switch Operation Notes BARSETU Base Aperture Page Index Offset Px SIZE Address Size Size (bits) (bits) Field (bits) 16 KB 512 B [63:14] [13:9] [8:0] 32 KB 1 KB [63:15] [14:10] [9:0] 64 KB 2 KB [63:16] [15:11] [10:0] 128 KB 4 KB...
Page 251: Id Translation
IDT Non-Transparent Switch Operation ID Translation Notes PCI Express TLPs may be categorized into request TLPs and completion TLPs. – A request TLP is a packet used to initiate a transaction. – A completion TLP is a packet used to terminate, or partially terminate a transaction sequence. Request TLPs contain a requester ID field that defines the unique PCI Express identifier associated with the requester that generated the request TLP.
Page 252 IDT Non-Transparent Switch Operation Notes Field Description Field Name Address Type Processing. This field specifies the processing of the address type (AT) field on request TLPs. Refer to section Address Type Processing on page 14- Completion No Snoop Processing. This field specifies the no snoop processing on completion TLPs.
Page 253: Request Id Translation
IDT Non-Transparent Switch Operation Notes ADDR TBLBASE Yes* TBLLIMIT > Protection Violation Mapping Table Entry * Yes means that (ADDR + TBLBASE) > TBLLIMIT Figure 14.6 NT Table Partitioning – The physical NT Mapping table entry accessed is equal to the sum of the partition NT Mapping table entry, specified by the ADDR field in the NTMTBLADDR register, with the TBLBASE field in the NTMTBLPROT register associated with the partition.
Page 254: Figure 14.7 Request Tlp Requester Id Translation
IDT Non-Transparent Switch Operation Notes The lookup is performed by matching the 16-bit requester ID in the request TLP along with the partition associated with the NT endpoint to entries in the NT Mapping table. If a lookup match is not found, then the TLP is treated as an unsupported request.
Page 255: Completion Id Translation
IDT Non-Transparent Switch Operation Notes • The bus field is replaced by the captured bus number of the NT endpoint associated with the partition of the translated TLP. • The device and function fields are replaced by the value 0x3. This corresponds to device 0, func- tion 3.
Page 256: Requester Id Capture Register
IDT Non-Transparent Switch Operation Notes If the Completion Enable (CPEN) bit is cleared in the NTCTL register of the NT endpoint associated with the translated TLP (i.e., in the destination partition), then the completion is silently dropped by the NT endpoint that received the request (i.e., in the source partition).
Page 257: Address Type Processing
IDT Non-Transparent Switch Operation Notes If the Completion No Snoop Processing (CNS) field in the NT Mapping entry corresponding to the extracted NT Mapping table index (see section Completion ID Translation on page 14-13) is set, then the No Snoop attribute in the translated TLP is inverted. If the CNS bit is cleared, then the No Snoop attribute in the translated TLP is equal to that of the received completion TLP (i.e., the No Snoop attribute is not modi- fied).
Page 258: Doorbell Registers
IDT Non-Transparent Switch Operation Doorbell Registers Notes Doorbells facilitate event signaling between partitions. Associated with each NT endpoint are one 32-bit outbound doorbell register and one 32-bit inbound doorbell register. An outbound doorbell request from an NT endpoint is initiated by writing a one to the corresponding bit in the Outbound Doorbell Set (OUTD- BELLSET) register.
Page 259: Message Registers
IDT Non-Transparent Switch Operation Notes Partition 0 Outbound Partition 1 Outbound Partition 7 Outbound Doorbell Bit x Doorbell Bit x Doorbell Bit x Global Outbound Doorbell Global Outbound Doorbell Global Outbound Doorbell Mask x, Bit 0 Mask x, Bit 1 Mask x, Bit 7 Global Inbound Doorbell Global Inbound Doorbell...
Page 260: Punch-Through Configuration Requests
IDT Non-Transparent Switch Operation Notes OUTMSGx Partition y SWPyMSGCTLx.PART Mapping Function SWPyMSGCTLx.REG Partition w INMSGz Figure 14.10 Logical Representation of Message Register Operation Since the mapping of outbound message registers to inbound message registers need not be one-to- one, it is possible to map multiple outbound message registers, from typically different partitions, to a single inbound message register.
Page 261: Re-Programming The Bus Number Of The Nt Function
IDT Non-Transparent Switch Operation Notes Punch-through requests are always emitted on the NT function’s link. In port operating modes with multiple functions (e.g., upstream switch port with NT function), it is not allowed for punch through requests issued by the NT function to hit the primary/secondary/subordinate window of the PCI-to-PCI bridge func- tion or the bus/device/function ID associated with other functions in the port.
Page 262: Interrupts
IDT Non-Transparent Switch Operation Notes Normally, devices with a PCI Express port capture the bus number associated with the port on reception of type 0 configuration write requests that target the port. In system scenarios where there is no root complex in the PCI Express hierarchy, the devices will not receive type 0 configuration write requests.
Page 263: Virtual Channel Support
IDT Non-Transparent Switch Operation Notes The interrupt sources each have a corresponding status bin in the NT Endpoint Interrupt Status (NTINTSTS) register. – When an interrupt source requests service, the corresponding bit in the NTINTSTS register is set. – An interrupt source may be masked from generating an interrupt by setting the corresponding mask bit in the NT Endpoint Interrupt Mask (NTINTMSK) register.
Page 264: Maximum Payload Size
IDT Non-Transparent Switch Operation Maximum Payload Size Notes The PES12NT12G2 requires that the Maximum Payload Size (MPS) field in the PCI Express Device Control (PCIEDCTL) register be set identically in all functions (i.e., PCI-to-PCI bridge, NT, and DMA) of a partition.
Page 265: Access Control Services (Acs)
IDT Non-Transparent Switch Operation Notes • When ECRC checking is not enabled in the NT endpoint, there is a possibility of silent data corruption on packets that cross the NTB (i.e., when a TLP with ECRC error is received by the NT endpoint, the NT endpoint does not check ECRC, and a new ECRC is re-computed by the NT endpoint in the destination partition, thereby “hiding”...
Page 266: Table 14.2 Acs Checks Performed By The Nt Function In A Port Operating In Multi-Function Mode
IDT Non-Transparent Switch Operation Notes PCI Express Error Base ACS Check Reporting Action Taken Specification Condition Section ACS Peer-to-Peer 6.12.1.1 Offending request is redirected upstream (P2P) Request (not an ACS viola- towards root complex. Redirect tion) ACS P2P Comple- Offending completion is redirected tion Redirect upstream towards root complex.
Page 267: Error Detection And Handling By The Nt Function
IDT Non-Transparent Switch Operation Notes Upstream Upstream Port Port ACS Peer-to- Peer Request Redirect Intended TLP Route ACS Re-directed Route Bridge Endpoint Endpoint Bridge Non Transparent Interconnect Partition 1 – Virtual PCI Bus Partition 2 – Virtual PCI Bus Bridge Bridge Bridge Bridge...
Page 268: Physical Layer Errors
IDT Non-Transparent Switch Operation Notes Some of the errors described below are marked as function-specific when the “function claims the TLP”. A function claims a TLP in the following cases: NT Endpoint function: – Address Routed TLPs: The TLP address falls within the address space range(s) programmed in the function’s base address registers (BARs).
Page 269: Table 14.4 Transaction Layer Errors Associated With The Nt Function
IDT Non-Transparent Switch Operation Notes Role Based PCI Express Function- (Advisory) Error Base Specific Error Action Taken Condition Specification Error Reporting Section Condition Poisoned TLP 2.7.2.2, 6.2.3.2.4.3 Advisory when Detected Parity Error bit received the correspond- (PCISTS.DPE) is set. ing error is con- If the poisoned TLP is a comple- figured as non- tion, the Master Data Parity Error...
Page 270 IDT Non-Transparent Switch Operation Notes Role Based PCI Express Function- (Advisory) Error Base Specific Error Action Taken Condition Specification Error Reporting Section Condition Completer abort 2.3.1 N/A (always Not applicable. The NT function non-advisory) does not issue completions with ‘Completer Abort’ status except for ACS violations.
Page 271: Table 14.5 Conditions Handled As Unsupported Requests (Ur) By The Nt Function
IDT Non-Transparent Switch Operation Notes PCI Express Conditions Handled as UR Description Base Specifica- tion Sect. Effective BAR Aperture check Refer to section BAR Limit on page 14-2. Lookup Table Address Translation Refer to section Lookup Table Address error: Translation on page 14-5. Table entry invalid, partition entry invalid, or out-of-bounds lookup table entry selected.
Page 272: Table 14.6 Conditions Handled As Unexpected Completion (Uc) By The Nt Function
IDT Non-Transparent Switch Operation Notes PCI Express Conditions Handled as Base Description Specification Section Non function-specific unexpected Port receives a completion TLP that is not claimed 6.2.4 completion by any function of the port. This is a non function- specific error and is therefore logged in all functions of the port.
Page 273: Ntb Inter-Partition Error Propagation
IDT Non-Transparent Switch Operation Notes The following function-specific errors require that the offending TLP’s header be logged in the NT func- tion’s AER capability structure. – Reception of a request that is unsupported and is claimed by the NT function. –...
Page 274 IDT Non-Transparent Switch Operation Notes When a TLP is routed across the PES12NT12G2 (within a partition or across partitions via the NTB), each function that receives the TLP checks for errors. Thus, it is possible that more than one function detect and report an error associated with the TLP.
Page 275 IDT Non-Transparent Switch Operation Malformed TLP Error Notes In the PES12NT12G2, malformed TLP errors are checked at the ingress port that receives the packet from the link, or at the egress port (if any) that transmits the packet. Malformed TLPs are nullified by the function that detects the error and thus no other functions in the logical path of the TLP will detect this type of error.
Page 276 IDT Non-Transparent Switch Operation Notes When the PCI-to-PCI bridge function in Partition 2 detects the UR error, it logs it as such and generates a completion TLP destined towards the NT Endpoint function associated with Partition 2. The completion TLP is then transferred across the NTB and transmitted by the NT Endpoint in Partition 1 towards the initi- ator of the request.
Page 277 IDT Non-Transparent Switch Operation Notes PCI-to-PCI bridge function of the upstream port in partition 2, and PCI-to-PCI bridge function of the down- stream switch port in partition 2) checks for UR errors. Also, notice that the request TLP logically stops at the PCI-to-PCI bridge function of the downstream switch port in partition 2 since this function detects the UR error.
Page 278: Table 14.9 Error Logging At Each Function For Poisoned Tlp Example
IDT Non-Transparent Switch Operation Notes Upstream Upstream Port Port Poisoned TLP’s Logical Path Bridge Endpoint Endpoint Bridge Non Transparent Interconnect Partition 1 – Virtual PCI Bus Partition 2 – Virtual PCI Bus Bridge Bridge Bridge Bridge Downstream Ports Figure 14.16 Poisoned TLP Error Propagation Example Table 14.9 shows the error logging for each function in the TLP’s logical path.
Page 279 IDT Non-Transparent Switch Operation Notes Function Error Logging NT Endpoint (Partition 2) Refer to row corresponding to ‘Poisoned TLP received’ in Table 14.4. In the table, this NT function is considered the “NT endpoint in the destination partition”. Upstream PCI-to-PCI Bridge (Partition 2) Refer to row corresponding to ‘Poisoned TLP received’...
Page 280: Figure 14.17 Example Of Combined Transaction Layer Error Handling
IDT Non-Transparent Switch Operation Notes that the non-posted TLP’s request is unsupported (e.g., the downstream switch port’s link is down). As a result, the downstream switch port handles the TLP as an supported request error and generates a comple- tion TLP with UR status. Upstream Upstream Port...
Page 281: Error Emulation Control In The Nt Function
IDT Non-Transparent Switch Operation Notes Function Error Logging NT Endpoint (Partition 2) Refer to row corresponding to ‘Poisoned TLP received’ in Table 14.4. In the table, this NT function is considered the “NT endpoint in the destination partition”. Additionally, refer to row corresponding to ‘Completion with UR status received’...
Page 282: Non Transparent Operation Restrictions
IDT Non-Transparent Switch Operation Notes Due to a limitation in the hardware, it is not possible to emulate the detection of a non-advisory uncor- rectable non-fatal error. Non Transparent Operation Restrictions The following lists usage restrictions associated with non-transparent operation. –...
Page 283: Dma Controller
Chapter 15 DMA Controller ® Overview Notes The PES12NT12G2 supports two direct memory access controller (DMA) functions. Each DMA function appears as a PCI Express endpoint in the PCI Express hierarchy, located in a partition’s upstream port. In each partition, the operating mode of the switch’s upstream port determines if this port contains a DMA function.
Page 284: Data Transfer And Addressing
IDT DMA Controller Notes DMA descriptors, DMA source addresses from where data is read, and DMA destination addresses to where data is written may be located anywhere in the PCI Express memory address space. – Memory holding DMA descriptors may be located above the upstream port, below a downstream switch port, or in another partition and accessed through an NT endpoint.
Page 285: Figure 15.2 Linear Addressing
IDT DMA Controller Notes The DMA supports two addressing modes: linear addressing and constant addressing. The simplest form of DMA addressing is linear addressing. In linear addressing, a sequential block of data consisting of BCOUNT bytes is transferred from a starting address SADDR to a destination address DADDR. Linear addressing is graphically illustrated in Figure 15.2.
Page 286: Table 15.1 Dma Channel Addressing Parameters
IDT DMA Controller Notes count = BCOUNT count = BCOUNT addr = SADDR addr = DADDR for (j=0; j<SSCOUNT; ++j) { for (j=0; j<DSCOUNT; ++j) { for (i=0; i<SSSIZE; ++i) { for (i=0; i<DSSIZE; ++i) { data = memRead(addr) memWrite(addr,data) count = count - 1 count = count - 1 if (count == 0) {...
Page 287: Table 15.2 Linear Addressing Dma Example
IDT DMA Controller Notes The programming of the addressing parameters must meet the following rules. 1. BCOUNT <= (SSCOUNT * SSSIZE) 2. (SSCOUNT * SSSIZE) = (DSCOUNT * DSSIZE) An addressing operation completes execution when the byte count is exhausted or, in case the above rules are violated, when stride addressing completes.
Page 288: Dma Descriptors
IDT DMA Controller Notes BCOUNT 1024 SADDR 0x0100_0000 DADDR 0x0200_0001 SSSIZE DSSIZE SSCOUNT DSCOUNT SSDIST DSDIST Table 15.3 Constant Addressing DMA Example SADDR DADDR BCOUNT PCI Express PCI Express Memory Address Memory Address Space Space Figure 15.5 Constant Addressing Example Note that the Source Stride Size (SSSIZE) determines the size of the region from which data is read.
Page 289: Figure 15.7 General Dma Descriptor Format
IDT DMA Controller Notes All DMA descriptors share the same common format shown in Figure 15.7. – DMA descriptors are eight DWords in size. – DMA descriptors must be DWord aligned. Processing by a channel of a DMA descriptor with an unaligned DWord address results in an error.
Page 290: Table 15.4 Stride Control Dma Descriptor Fields
IDT DMA Controller Notes 24 23 16 15 DTYPE DSTS DSSIZE SSSIZE SSCOUNT SSDIST Reserved DSDIST DSCOUNT Reserved NEXTL NEXTU Figure 15.8 Stride Control DMA Descriptor Format Field DWord Description Position SSSIZE 11:0 Source Stride Size. This field specifies the source stride in bytes.
Page 291 IDT DMA Controller Notes Field DWord Description Position Request Rate Update. When this bit is set, the DMA channel uses the value in the Request Rate (RR) field of this descriptor to update the DMA Channel Request Rate Control (DMACxR- RCTL) register.
Page 292: Table 15.5 Data Transfer Dma Descriptor Fields
IDT DMA Controller Notes 24 23 16 15 DTYPE DSTS MRRS BCOUNT SADDRL SADDRU DADDRL DADDRU NEXTL NEXTU Figure 15.9 Data Transfer DMA Descriptor Format Field DWord Description Position MRRS Maximum Read Request Size. This field specifies the maxi- mum DMA source read request size. 0000b - 1B 0001b - 2B 0010b - 4B...
Page 293 IDT DMA Controller Notes Field DWord Description Position Source Relaxed Ordering. This field specifies the state of the relaxed ordering attribute in source TLPs. Source No Snoop. This field specifies the state of the no snoop attribute in source TLPs. Interrupt on Finished.
Page 294 IDT DMA Controller Notes • The destination address may have any byte alignment. – The Byte Count (BCOUNT) field specifies the number of bytes to transfer. – The data transfer operation performed in processing the descriptor is controlled by DMA param- eters as described in section Data Transfer and Addressing on page 15-2.
Page 295: Table 15.6 Immediate Data Transfer Dma Descriptor Fields
IDT DMA Controller Notes pletions to memory write requests on the fly. As a result, the memory writes issued by the DMA may not arrive at the destination location in the order in which the read requests were issued. A user that wishes to keep a strict order between the order in which the bytes are read and written, may do so by programming the descriptor such that the address/length combination does not cross 4KB boundaries, and ensuring that the Byte Count (BCOUNT) field is less than or equal to the Maximum Read Request Size (MRRS)
Page 296 IDT DMA Controller Notes Field DWord Description Position Interrupt on Finished. When this bit is set and the DMA con- troller normally finishes processing of the descriptor, then the F bit is set in the corresponding channel DMA Status (DMAxS) register.
Page 297: Dma Descriptor Processing
IDT DMA Controller Notes • If the address is below 4 GB, then a MWr TLP with a 32-bit address is generated. If the address is above 4 GB, then a MWr TLP with a 64-bit address is generated. – The Byte Count (BCOUNT) field specifies the number of bytes to transfer. •...
Page 298 IDT DMA Controller Notes When the DMA channel halts descriptor processing it sets the Halt (H) bit in the DMA Channel Status (DMACxSTS) register and clears the Run (RUN) bit in the DMACxCTL register. – The DMACxDPTRL and DMACxDPTRH registers continue to hold the value of the last descriptor that was fetched.
Page 299: Table 15.7 Dma Chaining Disabling
IDT DMA Controller Notes Descriptor Descriptor Descriptor Descriptor DMAxDPTRH / DMAxDPTRL Descriptor Descriptor Descriptor Descriptor DMAxNDPTRH / DMAxNDPTRL Figure 15.11 DMA Chaining Example Writing to the DMACxNDPTRL/H registers while the DMA is running (i.e., the RUN bit is set in the DMACxCTL register) simply modifies the register value.
Page 300 IDT DMA Controller Notes Aborting a DMA Operation The processing of DMA descriptors by a DMA channel may be aborted by writing a one to the Abort (ABORT) bit in the DMACxCTL register. When a DMA operation is aborted due to this condition, the following actions take place: –...
Page 301: Table 15.8 Dma Channel Control (Dmacxctl) Register Action Summary
IDT DMA Controller Notes • All prefetched descriptors are discarded. – If the DMA channel is halted when suspended (i.e., the DMA has completed processing descrip- tors in a list), then the Suspend (S) bit in the DMACxSTS register is immediately set. Software should wait for the Suspend bit in the DMACxSTS register to be set prior to resuming the DMA channel as described next.
Page 302: Tlp Attribute And Traffic Class Control
IDT DMA Controller Notes After descriptors are appended to an active descriptor list, software must set the RUN bit in the DMACxCTL register . If the DMA channel had not initiated processing of the last descriptor in the original list at the time the RUN bit is set by software, the DMA channel continues processing descriptors normally, including the newly appended descriptors.
Page 303: Channel Interrupts
IDT DMA Controller Notes Data Transfer Attribute and Traffic Class Control The state of memory request TLP attributes and traffic class may be independently controlled for memory read and write operations on a descriptor by descriptor basis by fields in the data transfer DMA descriptor.
Page 304: Descriptor Prefetching
IDT DMA Controller Descriptor Prefetching Notes When the amount of data moved by data transfer descriptors is small (e.g., when moving data associ- ated with 64B packets), the overhead in fetching DMA descriptors from memory between data transfer operations may limit performance. To overcome this overhead, the DMA channel supports descriptor prefetching.
Page 305: Dma Multicast
IDT DMA Controller Notes It is possible to “in-line” request rate control information within a descriptor, using the Request Rate (RR) and Request Rate Update (RRU) fields in a stride descriptor (see section Stride Control Descriptor on page 15-7). This allows control of the request rate depending on the bandwidth of the source and destination devices associated with the DMA transfer.
Page 306: Figure 15.12 Path Taken By A Tlp Emitted By The Dma When It Is Multicasted
IDT DMA Controller Notes Upstream Port Path taken by Bridge Function the posted TLP emitted by the Virtual PCI Bus Bridge Bridge Bridge Bridge Bridge Downstream Ports Figure 15.12 Path Taken by a TLP Emitted by the DMA When it is Multicasted Upstream Port Port...
Page 307: Virtual Channel (Vc) Support
IDT DMA Controller Notes EN bit in INTXD bit Unmasked MSICAP in PCICMD Action Interrupt Register Register Asserted MSI message generated Assert_INTx message request generated None Negated None Deassert_INTx message request generated None Table 15.9 Downstream Switch Port Interrupts When the DMA function is configured to generate INTx messages, the specific INTx used (e.g., INTA, INTB, etc.) depends on the programming of the Interrupt Pin (INTRPIN) register.
Page 308: Table 15.10 Acs Checks Performed By The Dma Function
IDT DMA Controller Notes PCI Express Error Base ACS Check Reporting Action Taken Specification Condition Section ACS Peer-to-Peer 6.12.1.1 Offending request is redirected upstream Request Redirect (not an ACS viola- towards root complex. tion) ACS Peer-to-Peer This ACS check has no functional effect Completion Redirect in the switch, as described above.
Page 309: Power Management
IDT DMA Controller Notes Upstream Port Bridge Function Intended TLP Route ACS Redirected Route Virtual PCI Bus Bridge Bridge Bridge Bridge Bridge Downstream Ports Figure 15.14 Example of ACS Peer-to-Peer Request Redirect Applied by the DMA Function Refer to PCI Express Base Specification Revision 2.1 for further information on ACS. Power Management Refer to Chapter 9, Power Management.
Page 310: Pci Express Error Handling By The Dma Function
IDT DMA Controller Notes PCI Express errors are those specified in the PCI Express Base specification. DMA channel errors are additional proprietary errors associated with the operation of the DMA channels within the DMA function. PCI Express errors are described in section PCI Express Error Handling by the DMA Function on page 15- Internal switch errors (i.e., parity errors, switch time-out, and internal memory errors) are associated with the switch core and not with a specific port function.
Page 311 IDT DMA Controller Notes In addition, some of the errors described below are marked as function-specific when the “function claims the TLP”. Some of the errors described below are marked as function-specific when the “function claims the TLP”. A function claims a TLP in the following cases: –...
Page 312: Table 15.12 Pci Express Errors Detected By The Dma Function's Transaction Layer
IDT DMA Controller Notes Role Based Express Function- Channel- Error (Advisory) Base Specific Specific Action Taken Condition Error Spec Error Error Reporting Section Condition Poisoned TLP 2.7.2.2, See section Poisoned TLP received: Com- 6.2.3.2.4.3 (always non- Reception on page 15-32. pletion associ- advisory since Detected Parity Error bit...
Page 313 IDT DMA Controller Notes Role Based Express Function- Channel- Error (Advisory) Base Specific Specific Action Taken Condition Error Spec Error Error Reporting Section Condition Reception of a 2.3.1 ‘Yes’ if a Advisory Non-advisory case: uncorrect- request TLP that function when the cor- (DMA able error processing.
Page 314 IDT DMA Controller Notes Role Based Express Function- Channel- Error (Advisory) Base Specific Specific Action Taken Condition Error Spec Error Error Reporting Section Condition Flow control pro- 2.6.1 Not applicable. The DMA function does not check for any flow control protocol tocol error errors.
Page 315 IDT DMA Controller Notes When an ECRC error is detected, the header of the TLP with ECRC error is not utilized by the DMA channels for internal state computations (e.g., the channel’s outstanding byte count is not decremented, etc.) In cases where a received completion TLP has an ECRC error, this results in the DMA channel detecting a completion timeout error later in time.
Page 316 IDT DMA Controller Notes When the DMA function receives an expected completion with unsupported request (UR) status, and the completion is associated with a DMA channels outstanding data read request, the following actions are taken: – The affected DMA channel aborts descriptor processing and the Data Unsupported Request (DATUR) bit is set in the corresponding DMACxERRSTS register.
Page 317: Table 15.13 Prioritization Of Transaction Layer Errors
IDT DMA Controller Notes In addition, error pollution rules only apply to errors detected by the AER logic. The error bits in legacy PCI registers (e.g., PCI Status (PCISTS)) are not subject to AER error pollution rules. – For example, the Detected Parity Error (DPE) bit in the PCISTS register of the DMA function is set when the DMA function receives a poisoned TLP, even if error pollution rules result in a higher priority error (e.g., UR) being logged against the TLP.
Page 318: Dma Limitations And Usage Restrictions
IDT DMA Controller Notes TLP Received by DMA Function Done Handle per DMA Receiver Transaction Layer Error Overflow Error? Table Handle per DMA Receiver Transaction Layer Error Overflow Error? Table Handle per DMA ECRC Transaction Layer Error Error? Table Handle per DMA Malformed TLP? Transaction Layer Error Table...
Page 319: Switch Events
Chapter 16 Switch Events ® Overview Notes As described in section Switch Events on page 1-16, in a PCI Express switch with multiple partitions a need may exist to signal the occurrence of significant global events to a switch management agent. A need may also exist for communication between roots associated with different partitions as well as for communi- cation between these roots and a management agent.
Page 320: Link Up
IDT Switch Events Notes register controls which partitions are notified of the occurrence of an event. As mentioned above, each partition’s upstream port functions (i.e., PCI-to-PCI bridge and/or NT) may be configured to generate an interrupt to the system when an event is signaled to the partition. –...
Page 321: Link Down
IDT Switch Events Notes Associated with each status bit in the SELINKUPSTS register is a mask bit in the Switch Event Link Up Mask (SELINKUPMSK) register. When an unmasked status bit is set in the SELINKUPSTS register, the Link Up (LNKUP) status bit is set in the Switch Event Status (SESTS) register. Link Down A link down event occurs when a port’s data link status transitions from DL_Up to DL_Down.
Page 322: Global Signals
IDT Switch Events Global Signals Notes Global signals allow an agent in a switch partition to signal a switch event. This mechanism provides a primitive form of communication that allows an agent in a switch partitition to communicate with agents in other partitions.
Page 323: Port Aer Errors
IDT Switch Events Notes Within each NT function and upstream PCI-to-PCI bridge function is a general 32-bit read-write register that may be used to pass arbitrary data between an agent associated with a partition and agents in other partitions. – The NT Endpoint Signal Data (NTSDATA) register is this register in an NT function. –...
Page 324 IDT Switch Events Notes PES12NT12G2 User Manual 16 - 6 July 10, 2013...
Page 325: Multicast
Chapter 17 Multicast ® Overview Notes The PES12NT12G2 implements multicast within switch partitions as defined by the PCI Express Base Specification 2.1. The term transparent multicast is used to refer to this type of multicast operation. In addi- tion, the switch supports non-transparent multicast, using a proprietary implementation. This allows TLPs received by the NT endpoint to be multicasted to ports in other switch partitions.
Page 326 IDT Multicast Notes The following multicast register fields must be configured to the same value in all functions associated with a switch partition. Violating this requirement results in undefined behavior on receipt of a multicast TLP. Non-multicast TLPs are not affected. –...
Page 327: Figure 17.1 Multicast Group Address Ranges
IDT Multicast Notes 0x0000_0000_0000_0000 Muticast Base Address Multicast Group 0 INDEXPOS Multicast Group 1 Multicast Group 2 (NUMGROUP + 1) * 2 INDEXPOS Multicast Group 3 Multicast Group x 0xFFFF_FFFF_FFFF_FFFF Figure 17.1 Multicast Group Address Ranges The multicast address region associated with a TLP is determined as follows. –...
Page 328: Figure 17.2 Multicast Group Address Region Determination
IDT Multicast Notes Since bits in the multicast base address that correspond to the multicast group number or are less than the multicast index position (i.e., INDEXPOS) must be zero, the multicast group ID associated with a TLP may be determined as shown in Figure 17.2. –...
Page 329 IDT Multicast Notes Multicast TLP Routing A multicast TLP received without error by a function is forwarded as described in this section. Traditional unicast routing rules do not apply to multicast TLPs. Unlike unicast routing rules that depend on whether the TLP was received on the primary or secondary side of a PCI-to-PCI bridge and are thus different for upstream and downstream switch ports, multicast TLP routing is symmetric.
Page 330: Usage Restrictions
IDT Multicast Notes A side-effect of modifying the address due to multicast overlay processing is that the ECRC associated with the original TLP may not be correct for the new modified TLP. The PES12NT12G2 supports ECRC regeneration for multicast overlay. Therefore, functions perform the following ECRC processing.
Page 331: Nt Multicast Configuration
IDT Multicast Notes When the upstream port operates in a mode that contains an NT function but not a PCI-to-PCI bridge function (e.g., NT function mode, or NT with DMA function mode), NT multicast allows TLPs received by the NT function to be multicasted to ports in other partitions. When the upstream port operates in a mode that contains an NT and PCI-to-PCI bridge function, NT multicast co-exists with transparent multicast.
Page 332: Nt Multicast Tlp Determination
IDT Multicast Notes configured identically for transparent and NT multicast. But transparent and NT multicast configurations differ in their group/port associations. Specifically, transparent multicast groups are associated with ports within the switch partition, and NT multicast groups are associated with ports in other switch partitions. –...
Page 333: Nt Multicast Egress Processing
IDT Multicast Notes perform NT multicast egress processing (see section NT Multicast Egress Processing on page 17-9) and transmit the TLP on their data-link. The determination of which ports transmit the TLP is based on the following: – The received TLP’s multicast group ID. –...
Page 334 IDT Multicast Notes In order to perform NT multicast egress processing, each port contains four sets of NT multicast overlay registers, and each set is associated with a source partition and multicast group. Depending on the partition and group on which the NT multicast TLP is received, one of the four NT multicast overlay register sets is selected to control the manner in which the overlay operation is performed on the TLP.
Page 335: Usage Restrictions
IDT Multicast Notes When the OVRSIZE field value is six or greater, NT multicast address overlay processing is performed on all NT multicast TLPs transmitted by the port as described below. – Address bits in the NT multicast TLP with bit positions greater than or equal to OVRSIZE are replaced by the corresponding address bits in the multicast overlay base address.
Page 336 IDT Multicast Notes PES12NT12G2 User Manual 17 - 12 July 10, 2013...
Page 337: Temperature Sensor
Chapter 18 Temperature Sensor ® Overview Notes The PES12NT12G2 contains an on-chip temperature sensor that measures junction temperature. The sensor has three programmable temperature thresholds and a temperature history capability. An alarm is generated when the temperature is above or below one of three programmable temperature thresholds. –...
Page 338 IDT Temperature Sensor Notes PES12NT12G2 User Manual 18 - 2 July 10, 2013...
Page 339: Register Organization
Chapter 19 Register Organization ® Overview Notes All software visible registers in the switch are contained in a 512 KB global address space. The address of a register in this address range is referred to as the system address of the register. –...
Page 340 IDT Register Organization Notes Base Address Address Range 0x15000 Reserved 0x16000 Port 11 PCI-to-PCI Bridge Registers 0x17000 Reserved 0x18000 Reserved 0x19000 Reserved 0x1A000 Reserved 0x1B000 Reserved 0x1C000 Reserved 0x1D000 Reserved 0x1E000 Reserved 0x1F000 Reserved 0x20000 Port 16 PCI-to-PCI Bridge Registers 0x21000 Port 16 NT Endpoint Registers 0x22000...
Page 341: Partial-Byte Access To Word And Dword Registers
IDT Register Organization Notes registers associated with the NT function of a port (refer to section NT Function Registers on page 19-14). DMA endpoint registers correspond to the configuration registers associated with the DMA function of a port (refer to section DMA Function Registers on page 19-23). The switch configuration and status register region contains registers that control general operation of the switch and are proprietary in nature (e.g., registers to configure the switch ports and partitions, etc.).
Page 342: Address Maps
IDT Register Organization Address Maps Notes This section describes the address maps for regions of the global address space outlined in Table 19.1. Reserved address ranges are outlined in Figure 19.1. Reading from a reserved address range returns and undefined value. Writes to a reserved address range complete successfully and have an undefined behavior.
Page 343: Figure 19.1 Pci-To-Pci Bridge Configuration Space Organization
IDT Register Organization Notes 0x000 PCI Configuration Space (64 Dwords) 0x000 0x100 Advanced Error Reporting Enhanced Capability 0x180 Device Serial Number Enhanced Capability Type 1 Configuration Header 0x200 PCIe Virtual Channel Enhanced Capability 0x280 Power Budgeting Enhanced Capability 0x040 0x320 PCI Express Capability Structure ACS Enhanced Capability...
Page 344: Table 19.2 Pci-To-Pci Bridge Function Configuration Space Registers
IDT Register Organization The port operating mode (e.g., upstream switch port, downstream switch port, etc.) determines the presence of some configuration registers within the PCI-to-PCI bridge function’s configuration space. For example, the slot capability, slot control, and slot status registers are not present in the configuration space of a PCI-to-PCI bridge function associated with an upstream port.
Page 345 IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x022 Word MLIMIT MLIMIT - Memory Limit Register (0x022) on page 20-8 0x024 Word PMBASE PMBASE - Prefetchable Memory Base Register (0x024) on page 20-9 0x026 Word PMLIMIT PMLIMIT - Prefetchable Memory Limit Register (0x026) on page 20-9 0x028 DWord PMBASEU...
Page 346 IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x0D0 DWord MSICAP MSICAP - Message Signaled Interrupt Capability and Control (0x0D0) on page 20-37 0x0D4 DWord MSIADDR MSIADDR - Message Signaled Interrupt Address (0x0D4) on page 20-37 0x0D8 DWord MSIUADDR MSIUADDR - Message Signaled Interrupt Upper Address (0x0D8) on page 20-38...
Page 347 IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x324 Word ACSCAP ACSCAP - ACS Capability Register (0x324) on page 20-55 0x326 Word ACSCTL ACSCTL - ACS Control Register (0x326) on page 20-57 0x328 DWord ACSECV ACSECV - ACS Egress Control Vector (0x328) on page 20-58 0x330 DWord MCCAPH...
Page 348: Table 19.3 Default Linkage Of Capability Structures For A Pci-To-Pci Bridge Function In The Upstream Switch Port Mode
IDT Register Organization Default Value of Capability Next Capability Structure Name Space List Pointer Offset field (NXTPTR) PCI Express PCI Express Capability Structure 0x040 0x0C0 Capabilities List PCI Power Management Capability Structure 0x0C0 Message Signaled Interrupt Capability Structure 0x0D0 Subsystem ID and Subsystem Vendor ID 0x0F0 PCI Express Advanced Error Reporting (AER) Extended Capability...
Page 349: Proprietary Port-Specific Registers In The Pci-To-Pci Bridge Function
IDT Register Organization Proprietary Port-Specific Registers in the PCI-to-PCI Bridge Function This section outlines the address range 0x400 through 0xFFF in the configuration space of the PCI-to-PCI bridge function. This address range contains IDT proprietary registers that are port-specific (i.e., provide control or status on a per-port basis). These registers control proprietary function- ality or provide status beyond the functionality outlined in the PCI Express Base Specification.
Page 350: Figure 19.2 Proprietary Port Specific Register Organization
IDT Register Organization 0x400 Port Control & Status Registers 0x480 Internal Error Reporting Control & Status Registers 0x500 Physical Layer Registers 0x560 Reserved 0x700 Power Management Registers 0x880 Request Metering 0x890 Port Arbiter Controls 0x900 NT Multicast Overlay 0xD90 AER Error Emulation 0xE00 Reserved 0xFF8...
Page 351: Table 19.5 Proprietary Port Specific Registers
IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x400 DWord PORTCTL PORTCTL - Port Control (0x400) on page 21-1 0x404 DWord P2PINTSTS P2PINTSTS - PCI-to-PCI Bridge Interrupt Status (0x404) on page 21-1 0x408 DWord P2PINTMSK P2PINTMSK - PCI-to-PCI Bridge Interrupt Mask (0x408) on page 21-2 0x410 DWord P2PSDATA...
Page 352: Nt Function Registers
IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x908 DWord NTMCOVR0BARL NTMCOVR[3:0]BARL - NT Multicast Overlay x Base Address Low on page 21- 0x90C DWord NTMCOVR0BARH NTMCOVR[3:0]BARH - NT Multicast Overlay x Base Address High on page 21- 0x910 DWord NTMCOVR1C...
Page 353: Figure 19.3 Nt Function Configuration Space Organization
IDT Register Organization These registers are always accessible regardless of the port operating mode via the global address space access registers (i.e., GASAADDR and GASADATA), via the SMBus slave interface, or via serial EEPROM. Restrictions apply when using the GASAADDR and GASADATA registers. Refer to the definition of these registers for details.
Page 354: Table 19.6 Nt Function Registers
IDT Register Organization In order to facilitate PCI legacy software access to the PCI Express extended configuration space within the NT endpoint’s configuration space, the NT endpoint’s configuration space contains the Extended Configuration Space Access Address and Data registers (ECFGADDR and ECFGDATA). Refer to the definition of these registers for further details.
Page 355 IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x034 Byte CAPPTR CAPPTR - Capabilities Pointer (0x034) on page 22-11 0x03C Byte INTRLINE INTRLINE - Interrupt Line (0x03C) on page 22-12 0x03D Byte INTRPIN INTRPIN - Interrupt PIN (0x03D) on page 22-12 0x03E Byte MINGNT...
Page 356 IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x10C DWord AERUESV AERUESV - AER Uncorrectable Error Severity (0x10C) on page 22-37 0x110 DWord AERCES AERCES - AER Correctable Error Status (0x110) on page 22-39 0x114 DWord AERCEM AERCEM - AER Correctable Error Mask (0x114) on page 22-40 0x118 DWord AERCTL...
Page 357 IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x408 DWord NTINTMSK NTINTMSK - NT Endpoint Interrupt Mask (0x408) on page 22-55 0x40C DWord NTSDATA NTSDATA - NT Endpoint Signal Data (0x40C) on page 22-55 0x410 DWord NTGSIGNAL NTGSIGNAL - NT Endpoint Global Signal (0x410) on page 22-56 0x414 DWord NTIERRORMSK0...
Page 358 IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x494 DWord BARLIMIT2 BARLIMIT2 - BAR 2 Limit Address (0x494) on page 22-74 0x498 DWord BARLTBASE2 BARLTBASE2 - BAR 2 Lower Translated Base Address (0x498) on page 22-74 0x49C DWord BARUTBASE2 BARUTBASE2 - BAR 2 Upper Translated Base Address (0x49C) on page 22-75...
Page 359: Table 19.7 Default Linkage Of Capability Structures For The Nt Function When Operating As Function 0 Of The Port
IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x600 DWord NTMCG0PA NTMCG[3:0]PA - NT Multicast Group x Port Association (0x600-60C) on page 22-93 0x604 DWord NTMCG1PA NTMCG[3:0]PA - NT Multicast Group x Port Association (0x600-60C) on page 22-93 0x608 DWord NTMCG2PA...
Page 360: Table 19.8 Default Linkage Of Capability Structures For The Nt Function When Operating As Function 1 Of The Port
IDT Register Organization Default Value of Capability Next Capability Structure Name Space List Pointer Offset field (NXTPTR) PCI Express Advanced Error Reporting (AER) Extended Capability 0x100 0x200 Extended Capa- Device Serial Number Extended Capability 0x180 bilities List PCI Express Virtual Channel Capability 0x200 0x330 ACS Extended Capability...
Page 361: Dma Function Registers
IDT Register Organization DMA Function Registers This section outlines the configuration space associated the DMA function. These registers are accessible via PCI Express configuration requests to function 2 when the port is configured to operate in the following modes: – Upstream switch port with DMA function –...
Page 362: Figure 19.4 Dma Function Configuration Space Organization
IDT Register Organization 0x000 PCI Configuration Space (64 Dwords) 0x000 0x100 Advanced Error Reporting Enhanced Capability Type 0 Configuration Header Reserved 0x040 0x320 PCI Express Capability Structure ACS Enhanced Capability BAR Configuration 0x400 0x408 AER Error Emulation Internal Error Reporting 0x410 Masks Reserved...
Page 363: Table 19.10 Dma Function Registers
IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x000 Word VID - Vendor Identification (0x000) on page 23-1 0x002 Word DID - Device Identification (0x002) on page 23-1 0x004 Word PCICMD PCICMD - PCI Command (0x004) on page 23-1 0x006 Word PCISTS...
Page 364 IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x06C DWord PCIELCAP2 PCIELCAP2 - PCI Express Link Capabilities 2 (0x06C) on page 23-20 0x070 Word PCIELCTL2 PCIELCTL2 - PCI Express Link Control 2 (0x070) on page 23-20 0x072 Word PCIELSTS2 PCIELSTS2 - PCI Express Link Status 2 (0x072) on page 23-21 0x0C0...
Page 365 IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x508 DWord DMAC0STS DMAC[1:0]STS - DMA Channel Status (0x508/608) on page 23-50 0x50C DWord DMAC0MSK DMAC[1:0]MSK - DMA Channel Status Mask (0x50C/60C) on page 23-51 0x510 DWord DMAC0ERRSTS DMAC[1:0]ERRSTS - DMA Channel Error Status (0x510/610) on page 23-52 0x514 DWord DMAC0ERRMSK...
Page 366: Switch Configuration And Status Registers
IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x634 DWord DMAC1NDPTRH DMAC[1:0]NDPTRH - DMA Channel Next Descriptor Pointer High (0x534/634) on page 23-57 0xFF8 DWord GASAADDR GASAADDR - Global Address Space Access Address (0xFF8) on page 23-57 0xFFC DWord GASADATA GASADATA - Global Address Space Access Data (0xFFC) on page 23-58...
Page 367: Figure 19.5 Switch Configuration And Status Space Organization
IDT Register Organization 0x0000 Switch Control & Status 0x0010 Stack Configuration 0x0080 Internal Switch Timers 0x0100 Switch Partition & Port Configuration Registers 0x0500 Failover Capability 0x0700 Protection Registers 0x07F0 Reserved 0x0C00 Switch Event & Signals Registers 0x0C3C Global Doorbell Registers 0x0E00 Global Message Registers 0x1000...
Page 368: Table 19.11 Switch Configuration And Status
IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x0000 DWord SWCTL SWCTL - Switch Control (0x0000) on page 24-1 0x0004 DWord BCVSTS BCVSTS - Boot Configuration Vector Status (0x0004) on page 24-2 0x0008 DWord PCLKMODE PCLKMODE - Port Clocking Mode (0x0008) on page 24-3 0x0010 DWord STK0CFG...
Page 369 IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x0284 DWord SWPORT4STS SWPORT[19:16,11:8,3:0]STS - Switch Port x Status on page 24-9 0x0288 DWord SWPORT4FCTL SWPORT[19:16,11:8,3:0]FCTL - Switch Port x Failover Control on page 24-11 0x02A0 DWord SWPORT5CTL SWPORT[19:16,11:8,3:0]CTL - Switch Port x Control on page 24-8 0x02A4 DWord SWPORT5STS...
Page 370 IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x0404 DWord SWPORT16STS SWPORT[19:16,11:8,3:0]STS - Switch Port x Status on page 24-9 0x0408 DWord SWPORT16FCTL SWPORT[19:16,11:8,3:0]FCTL - Switch Port x Failover Control on page 24-11 0x0420 DWord SWPORT17CTL SWPORT[19:16,11:8,3:0]CTL - Switch Port x Control on page 24-8 0x0424 DWord SWPORT17STS...
Page 371 IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x0710 DWord NTMTBLPROT0 GASAPROT - Global Address Space Access Protection (0x0700) on page 24-14 0x0714 DWord NTMTBLPROT1 NTMTBLPROT[3:0] - Partition x NT Mapping Table Protection on page 24-14 0x0718 DWord NTMTBLPROT2 NTMTBLPROT[3:0] - Partition x NT Mapping Table Protection on page 24-14 0x071C...
Page 372 IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x0D44 DWord GODBELLMSK17 GODBELLMSK[31:0] - NT Global Outbound Doorbell Mask [31:0] on page 24-22 0x0D48 DWord GODBELLMSK18 GODBELLMSK[31:0] - NT Global Outbound Doorbell Mask [31:0] on page 24-22 0x0D4C DWord GODBELLMSK19 GODBELLMSK[31:0] - NT Global Outbound Doorbell Mask [31:0] on page 24-22 0x0D50...
Page 373 IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x0DD4 DWord GIDBELLMSK21 GIDBELLMSK[31:0] - NT Global Inbound Doorbell Mask [31:0] on page 24-23 0x0DD8 DWord GIDBELLMSK22 GIDBELLMSK[31:0] - NT Global Inbound Doorbell Mask [31:0] on page 24-23 0x0DDC DWord GIDBELLMSK23 GIDBELLMSK[31:0] - NT Global Inbound Doorbell Mask [31:0] on page 24-23 0x0DE0...
Page 374 IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x1044 DWord S2TXLCTL0 S[7:0]TXLCTL0 - SerDes x Transmitter Lane Control 0 on page 24-25 0x1048 DWord S2TXLCTL1 S[7:0]TXLCTL1 - SerDes x Transmitter Lane Control 1 on page 24-27 0x1050 DWord S2RXEQLCTL S[7:0]RXEQLCTL - SerDes x Receiver Equalization Lane Control on page 24-30 0x1060...
Page 375 IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x11AC DWord IOEXPADDR5 IOEXPADDR5 - SMBus I/O Expander Address 5 (0x11AC) on page 24-42 0x11B0 DWord GPECTL GPECTL - General Purpose Event Control (0x11B0) on page 24-42 0x11B4 DWord GPESTS GPESTS - General Purpose Event Status (0x11B4) on page 24-43 0x11D4 DWord...
Page 376 IDT Register Organization PES12NT12G2 User Manual 19 - 38 July 10, 2013...
Page 377: Pci-To-Pci Bridge Registers
Chapter 20 PCI-to-PCI Bridge Registers ® Type 1 Configuration Header Registers Notes VID - Vendor Identification Register (0x000) Field Default Type Description Field Name Value 15:0 0x111D Vendor Identification. This field contains the 16-bit vendor ID value assigned to IDT. See section Vendor ID on page 1-1.
Page 378 IDT PCI-to-PCI Bridge Registers Notes PCICMD - PCI Command Register (0x004) Field Default Type Description Field Name Value IOAE I/O Access Enable. When this bit is cleared, the bridge function does not respond to I/O accesses from the primary bus specified by IOBASE and IOLIMIT.
Page 379 IDT PCI-to-PCI Bridge Registers Notes Field Default Type Description Field Name Value FB2B Fast Back-to-Back Enable. Not applicable. INTXD INTx Disable. Controls the ability of the PCI-to-PCI bridge to generate an INTx interrupt message. When this bit is set, any interrupts generated by this bridge are negated.
Page 380 IDT PCI-to-PCI Bridge Registers Notes Field Default Type Description Field Name Value RTAS Received Target Abort. Not applicable (the bridge never generates requests on its own behalf). RMAS Received Master Abort. Not applicable (the bridge never generates requests on its own behalf).
Page 381 IDT PCI-to-PCI Bridge Registers Notes CLS - Cache Line Size Register (0x00C) Field Default Type Description Field Name Value 0x00 Cache Line Size. This field has no effect on the bridge’s functionality but may be read and written by software. This field is implemented for compatibility with legacy soft- ware.
Page 382 IDT PCI-to-PCI Bridge Registers Notes BAR1 - Base Address Register (0x014) Field Default Type Description Field Name Value 31:0 Base Address Register. Not applicable. PBUSN - Primary Bus Number Register (0x018) Field Default Type Description Field Name Value PBUSN Primary Bus Number. This field is used to record the bus number of the PCI bus segment to which the primary interface of the bridge is con- nected.
Page 383 IDT PCI-to-PCI Bridge Registers Notes IOBASE - I/O Base Register (0x01C) Field Default Type Description Field Name Value IOCAP I/O Capability. SWSticky Indicates if the bridge supports 16-bit or 32-bit I/O address- ing. 0x0 - (io16) 16-bit I/O addressing. 0x1 - (io32) 32-bit I/O addressing. Reserved Reserved field.
Page 384 IDT PCI-to-PCI Bridge Registers Notes Field Default Type Description Field Name Value STAS RW1C Signaled Target Abort Status. This bit is set when the bridge completes a posted or non- posted request with a completer-abort error on its second- ary side .
Page 385 IDT PCI-to-PCI Bridge Registers Notes PMBASE - Prefetchable Memory Base Register (0x024) Field Default Type Description Field Name Value PMCAP Prefetchable Memory Capability. SWSticky Indicates if the bridge supports 32-bit or 64-bit prefetchable memory addressing. 0x0 - (prefmem32) 32-bit prefetchable memory addressing. 0x1 - (prefmem64) 64-bit prefetchable memory addressing.
Page 386 IDT PCI-to-PCI Bridge Registers Notes PMLIMITU - Prefetchable Memory Limit Upper Register (0x02C) Field Default Type Description Field Name Value 31:0 PMLIMITU Prefetchable Memory Address Limit Upper. This field specifies the upper 32-bits of PMLIMIT. When the PMCAP field in the PMBASE register is cleared, this field becomes read-only with a value of zero.
Page 387 IDT PCI-to-PCI Bridge Registers Notes INTRLINE - Interrupt Line Register (0x03C) Field Default Type Description Field Name Value INTRLINE Interrupt Line. This register communicates interrupt line routing informa- tion. Values in this register are programmed by system soft- ware and are system architecture specific. This function does not use the value in this register.
Page 388 IDT PCI-to-PCI Bridge Registers Notes BCTL - Bridge Control Register (0x03E) Field Default Type Description Field Name Value PERRE Parity Error Response Enable. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit (MDPED) in the Secondary Status (SECSTS) register.
Page 389: Pci Express Capability Structure
IDT PCI-to-PCI Bridge Registers Notes Field Default Type Description Field Name Value Reserved Reserved field. SRESET Secondary Bus Reset. Setting this bit triggers a secondary bus reset. In the upstream port, setting this bit initiates a Upstream Secondary Bus Reset. In a downstream switch port, setting this bit initiates a Downstream Secondary Bus Reset.
Page 390 IDT PCI-to-PCI Bridge Registers Notes PCIEDCAP - PCI Express Device Capabilities (0x044) Field Default Type Description Field Name Value MPAYLOAD HWINIT Maximum Payload Size Supported. (See This field indicates the maximum payload size that the description) device can support for TLPs. MSWSticky The default value of this field is automatically set by the hardware based on the port’s maximum link width as deter-...
Page 391 IDT PCI-to-PCI Bridge Registers Notes Field Default Type Description Field Name Value Power Indicator Present. In PCI Express Specification 1.0a when set, this bit indi- cates that a Power Indicator is implemented on the card/ module. The value of this field is undefined in the PCI Express Base Specification.
Page 392 IDT PCI-to-PCI Bridge Registers Notes PCIEDCTL - PCI Express Device Control (0x048) Field Default Type Description Field Name Value CEREN Correctable Error Reporting Enable. This bit controls reporting of correctable errors by this func- tion. NFEREN Non-Fatal Error Reporting Enable. This bit controls reporting of non-fatal errors by this func- tion.
Page 393 IDT PCI-to-PCI Bridge Registers Notes Field Default Type Description Field Name Value Enable No Snoop. Not applicable. The bridge function does not generate transactions with the No Snoop bit set and passes transac- tions through the bridge with the No Snoop bit unmodified. 14:12 MRRS Maximum Read Request Size.
Page 394 IDT PCI-to-PCI Bridge Registers Notes PCIELCAP - PCI Express Link Capabilities (0x04C) Field Default Type Description Field Name Value MAXLNKSPD Maximum Link Speed. SWSticky This field indicates the supported link speeds of the port. (gen1) 2.5 GT/s (gen2) 5 GT/s others - reserved Note: This device advertises support for 5 GT/s regardless of the setting of this field.
Page 395 IDT PCI-to-PCI Bridge Registers Notes Field Default Type Description Field Name Value 17:15 L1EL L1 Exit Latency. SWSticky This field indicates the L1 exit latency for the given PCI Express link. Transitioning from L1 to L0 always requires approximately 2.3 µS. Therefore, a value 2 µs to less than 4 µs is reported with a default value of 0x2.
Page 396 IDT PCI-to-PCI Bridge Registers Notes PCIELCTL - PCI Express Link Control (0x050) Field Default Type Description Field Name Value ASPM Active State Power Management (ASPM) Control. This field controls the level of ASPM supported by the link. The initial value corresponds to disabled. 0x0 - (disabled) disabled 0x1 - (l0s) L0s enable entry 0x2 - (l1) L1 enable entry...
Page 397 IDT PCI-to-PCI Bridge Registers Notes Field Default Type Description Field Name Value CCLK Common Clock Configuration. When set, this bit indicates that this port and the port at the opposite end of the link are operating with a distributed common reference clock. When a port operates in a multi-function mode, software must set this bit identically for all functions of the port.
Page 398 IDT PCI-to-PCI Bridge Registers Notes PCIELSTS - PCI Express Link Status (0x052) Field Default Type Description Field Name Value Current Link Speed. This field indicates the current link speed of the port. (gen1) 2.5 GT/s (gen2) 5 GT/s others - reserved HWINIT Negotiated Link Width.
Page 399 IDT PCI-to-PCI Bridge Registers Notes Field Default Type Description Field Name Value DLLLA Data Link Layer Link Active. This bit indicates the status for the data link control and management state machine. 0x0 - (not_active) Data link layer not active state 0x1 - (active) Data link layer active state This bit is never be set by hardware if the DLLLA bit in the PCIELCAP register is cleared.
Page 400 IDT PCI-to-PCI Bridge Registers Notes PCIESCAP - PCI Express Slot Capabilities (0x054) Field Default Type Description Field Name Value Attention Button Present. SWSticky This bit is set when the Attention Button is implemented for the port. This bit is read-only and has a value of zero when the SLOT bit in the PCIECAP register is cleared.
Page 401 IDT PCI-to-PCI Bridge Registers Notes Field Default Type Description Field Name Value 16:15 SPLS Slot Power Limit Scale. This field specifies the scale used for the Slot Power Limit Value (SPLV). 0x0 - (x1) 1.0x 0x1 - (xp1) 0.1x 0x2 - (xp01) 0.01x 0x3 - (xp001) 0.001x A Set_Slot_Power_Limit message is generated using this field whenever this register is written or when the link transi-...
Page 402 IDT PCI-to-PCI Bridge Registers Notes PCIESCTL - PCI Express Slot Control (0x058) Field Default Type Description Field Name Value ABPE HWINIT Attention Button Pressed Enable. This bit when set enables generation of a Hot-Plug interrupt or wake-up event on an attention button pressed event. This bit is read-only and has a value of zero when the corre- sponding capability is not enabled in the PCIESCAP regis- ter.
Page 403 IDT PCI-to-PCI Bridge Registers Notes Field Default Type Description Field Name Value CCIE HWINIT Command Complete Interrupt Enable. This bit when set enables the generation of a Hot-Plug interrupt when a command is completed by the Hot-Plug Controller. When the corresponding capability is enabled, the initial value of this field after a partition fundamental reset is equal to the value of the corresponding field in the PCIESCTLIV register.
Page 404 IDT PCI-to-PCI Bridge Registers Notes Field Default Type Description Field Name Value HWINIT Power Indicator Control. When read, this register returns the current state of the Power Indicator. Writing to this register sets the indicator. This bit is read-only and has a value of zero when the corre- sponding capability is not enabled in the PCIESCAP regis- ter.
Page 405 IDT PCI-to-PCI Bridge Registers Notes PCIESSTS - PCI Express Slot Status (0x05A) Field Default Type Description Field Name Value RW1C Attention Button Pressed. Set when the attention button is pressed. RW1C Power Fault Detected. Set when the Power Controller detects a power fault. MRLSC RW1C MRL Sensor Changed.
Page 406 IDT PCI-to-PCI Bridge Registers Notes Field Default Type Description Field Name Value Electromechanical Interlock Status. When an electromechanical interlock is implemented, this bit indicates the current status of the interlock. The status of this bit is determined by the state of the corre- sponding PxILOCKST input signal on the I/O expander.
Page 407 IDT PCI-to-PCI Bridge Registers Notes Field Default Type Description Field Name Value LTRMS LTR Mechanism Supported. The switch does not support the Latency Tolerance Report- ing mechanism. 13:12 TPHCS TPH Completer Supported. Not applicable. 19:14 Reserved Reserved field. EFMTFS Extended Fmt Field Supported. The switch does not support the 3-bit definition of the FMT field in TLPs.
Page 408 IDT PCI-to-PCI Bridge Registers Notes PCIEDSTS2 - PCI Express Device Status 2 (0x06A) Field Default Type Description Field Name Value 15:0 Reserved Reserved field. PCIELCAP2 - PCI Express Link Capabilities 2 (0x06C) Field Default Type Description Field Name Value 31:0 Reserved Reserved field.
Page 409 IDT PCI-to-PCI Bridge Registers Notes Field Default Type Description Field Name Value Selectable De-emphasis. SWSticky For a downstream switch port, this bit sets the de-emphasis level when the link operates at 5.0 GT/s. Per the PCI Express Base Specification, this bit is not appli- cable for upstream ports.
Page 410 IDT PCI-to-PCI Bridge Registers Notes Field Default Type Description Field Name Value Enter Modified Compliance. Sticky When this bit is set to 1b, the port transmits the modified compliance pattern if the LTSSM enters Polling.Compliance state. This register is intended for debug, compliance testing pur- poses only.
Page 411: Pci Power Management Capability Structure
IDT PCI-to-PCI Bridge Registers Notes PCIESSTS2 - PCI Express Slot Status 2 (0x07A) Field Default Type Description Field Name Value 15:0 Reserved Reserved field. PCI Power Management Capability Structure PMCAP - PCI Power Management Capabilities (0x0C0) Field Default Type Description Field Name Value...
Page 412 IDT PCI-to-PCI Bridge Registers Notes PMCSR - PCI Power Management Control and Status (0x0C4) Field Default Type Description Field Name Value PSTATE Power State. This field is used to determine the current power state of the function and to set a new power state. 0x0 - (d0) D0 state 0x1 - (d1) D1 state (not supported by the switch and reserved)
Page 413 IDT PCI-to-PCI Bridge Registers Message Signaled Interrupt Capability Structure Notes MSICAP - Message Signaled Interrupt Capability and Control (0x0D0) Field Default Type Description Field Name Value CAPID Capability ID. The value of 0x5 identifies this capability as a MSI capabil- ity structure.
Page 414: Subsystem Id And Subsystem Vendor Id
IDT PCI-to-PCI Bridge Registers Notes MSIUADDR - Message Signaled Interrupt Upper Address (0x0D8) Field Default Type Description Field Name Value 31:0 UADDR Upper Message Address. This field specifies the upper portion of the DWORD address of the MSI memory write transaction. If the con- tents of this field are non-zero, then 64-bit address is used in the MSI memory write transaction.
Page 415: Extended Configuration Space Access Registers
IDT PCI-to-PCI Bridge Registers Notes SSIDSSVID - Subsystem ID and Subsystem Vendor ID (0x0F4) Field Default Type Description Field Name Value 15:0 SSVID Subsystem Vendor ID. SWSticky This field identifies the manufacturer of the add-in card or subsystem. SSVID values are assigned by the PCI-SIG to insure uniqueness.
Page 416: Advanced Error Reporting (Aer) Extended Capability
IDT PCI-to-PCI Bridge Registers Notes ECFGDATA - Extended Configuration Space Access Data (0x0FC) Field Default Type Description Field Name Value 31:0 DATA Configuration Data. A read from this field will return the configuration space reg- ister value pointed to by the ECFGADDR register. A write to this field will update the contents of the configuration space register pointed to by the ECFGADDR register with the value written.
Page 417 IDT PCI-to-PCI Bridge Registers Notes Field Default Type Description Field Name Value SDOENERR Upstre Surprise Down Error Status. Sticky This bit is set when a surprise down error is detected and Port: the SDERR bit in the PCIELCAP register is set. This bit is not applicable for an upstream port.
Page 418 IDT PCI-to-PCI Bridge Registers Notes Field Default Type Description Field Name Value MCBLKTLP RW1C MC Blocked TLP Status. Sticky This bit is set when a multicast TLP is blocked by this func- tion in response to the setting of the MC_Block_All and MC_Block_Untranslated bits in the multicast extended capability structure.
Page 419 IDT PCI-to-PCI Bridge Registers Notes Field Default Type Description Field Name Value FCPERR Flow Control Protocol Error Mask. Not applicable. COMPTO Completion Timeout Mask. Not applicable. CABORT Completer Abort Mask. Not applicable. UECOMP Unexpected Completion Mask. Sticky When this bit is set, the corresponding bit in the AERUES register is masked.
Page 420 IDT PCI-to-PCI Bridge Registers Notes Field Default Type Description Field Name Value ACSV ACS Violation Mask. Sticky When this bit is set, the corresponding bit in the AERUES register is masked. When a bit is masked in the AERUES register, the corresponding event is not logged in the advanced capability structure, the First Error Pointer field (FEPTR) in the AERCTL register is not updated, and an error is not reported to the root complex.
Page 421 IDT PCI-to-PCI Bridge Registers Notes Field Default Type Description Field Name Value SDOENERR Upstre Surprise Down Error Severity. Sticky This bit controls the severity of the reported error. If this bit Port: is set, the event is reported as a fatal error. When this bit is cleared, the event is reported as a non-fatal error.
Page 422 IDT PCI-to-PCI Bridge Registers Notes Field Default Type Description Field Name Value Uncorrectable Internal Error Severity. Sticky This bit controls the severity of the reported error. If this bit is set, the event is reported as a fatal error. When this bit is cleared, the event is reported as a non-fatal error.
Page 423 IDT PCI-to-PCI Bridge Registers Notes Field Default Type Description Field Name Value RW1C Correctable Internal Error Status. Sticky This bit is set whenever an correctable internal error associ- ated with the port is detected. When the Internal Error Reporting Enable (IERROREN) bit is cleared in the Internal Error Reporting Control (IER- RORCTL) register, this field becomes read-only with a value of zero.
Page 424 IDT PCI-to-PCI Bridge Registers Notes Field Default Type Description Field Name Value RPLYROVR Replay Number Rollover Mask. Sticky When this bit is set, the corresponding bit in the AERCES register is masked. When a bit is masked in the AERCES register, the corresponding event is not reported to the root complex.
Page 425 IDT PCI-to-PCI Bridge Registers Notes AERCTL - AER Capabilities and Control (0x118) Field Default Type Description Field Name Value FEPTR First Error Pointer. Sticky This field contains a pointer to the bit in the AERUES regis- ter that resulted in the first reported error. This field is valid only when the bit in the AERUES register pointed to by this field is set.
Page 426: Device Serial Number Extended Capability
IDT PCI-to-PCI Bridge Registers Notes AERHL3DW - AER Header Log 3rd Doubleword (0x124) Field Default Type Description Field Name Value 31:0 Header Log. Sticky This field contains the 3rd doubleword of the TLP header that resulted in the first reported uncorrectable error. AERHL4DW - AER Header Log 4th Doubleword (0x128) Field Default...
Page 427: Pci Express Virtual Channel Capability
IDT PCI-to-PCI Bridge Registers Notes SNUMUDW - Serial Number Upper Doubleword (0x188) Field Default Type Description Field Name Value 31:0 SNUM Upper 32-bits of Device Serial Number. SWSticky This field contains the upper 32-bits of the IEEE defined 64- bit extended unique identifier (EUI-64) assigned to the device.
Page 428 IDT PCI-to-PCI Bridge Registers Notes Field Default Type Description Field Name Value Reserved Reserved field. REFCLK Reference Clock. Not supported (i.e., Time-based WRR Port Arbitration is not implemented). 11:10 PATBLSIZ Port Arbitration Table Entry Size. This field indicates the size of the port arbitration table. This function only supports hardware fixed round-robin, so the port arbitration table is not implemented.
Page 429 IDT PCI-to-PCI Bridge Registers Notes VCR0CAP- VC Resource 0 Capability (0x210) Field Default Type Description Field Name Value PARBC Port Arbitration Capability. This field indicates the type of port arbitration supported by this VC resource. Each bit corresponds to a port arbitration capability.
Page 430: Acs Extended Capability
IDT PCI-to-PCI Bridge Registers Notes Field Default Type Description Field Name Value 26:24 VCID VC ID. This field assigns a VC ID to the VC resource. For VC0, this field is always hardwired to zero. 30:27 Reserved Reserved field. VCEN VC Enable.
Page 431 IDT PCI-to-PCI Bridge Registers Notes ACSCAP - ACS Capability Register (0x324) Field Default Type Description Field Name Value Upstream ACS Source Validation. Port: If set, indicates that this function implements ACS Source Validation. This field must never be set to 0x1 in an upstream port. Down- stream Switch Port:...
Page 432 IDT PCI-to-PCI Bridge Registers Notes Field Default Type Description Field Name Value Upstream ACS P2P Egress Control. Port: If set, indicates that this function implements ACS Peer-to- Peer Egress Control. For a downstream switch port, peer- to-peer refers to transfers among downstream switch ports Down- in the same partition.
Page 433 IDT PCI-to-PCI Bridge Registers Notes ACSCTL - ACS Control Register (0x326) Field Default Type Description Field Name Value Upstre ACS Source Validation Enable. When set, this function performs ACS Source Validation. Port: Note: This field becomes read-only-zero when the corre- sponding bit in the ACSCAP register is cleared.
Page 434 IDT PCI-to-PCI Bridge Registers Notes Field Default Type Description Field Name Value Upstre ACS P2P Egress Control Enable. When set, this function performs ACS Peer-to-Peer Egress Port: Control. Note: This field becomes read-only-zero when the corre- sponding bit in the ACSCAP register is cleared. Down- stream Switch...
Page 435: Multicast Extended Capability
IDT PCI-to-PCI Bridge Registers Multicast Extended Capability Notes MCCAPH - Multicast Extended Capability Header (0x330) Field Default Type Description Field Name Value 15:0 CAPID 0x12 Capability ID. The value of 0x12 indicates a multicast capability structure. 19:16 CAPVER Capability Version. The value of 0x1 indicates compatibility with the PCI Express Base Specification.
Page 436 IDT PCI-to-PCI Bridge Registers Notes MCCTL- Multicast Control (0x336) Field Default Type Description Field Name Value NUMGROUP Number of Multicast Groups. When the Multicast Enabler (MEN) bit is set, this field indi- cates the number of multicast groups that are enabled. The number of groups enabled is equal to the value in this field plus one.
Page 437 IDT PCI-to-PCI Bridge Registers Notes MCBARH- Multicast Base Address High (0x33C) Field Default Type Description Field Name Value 31:0 MCBARH Multicast BAR High. This field specifies the upper 32-bits (i.e., bits 32 through 63) of the multicast BAR. The behavior is undefined if bits in this field corresponding to address bits that contain the multicast group number or those less than the multicast index position (i.e., INDEX- POS) are non-zero.
Page 438 IDT PCI-to-PCI Bridge Registers Notes MCBLKALLL- Multicast Block All Low (0x348) Field Default Type Description Field Name Value 31:0 MCBLKALL Multicast Block All. Each bit in this field corresponds to one of the lower 32 mul- ticast groups (e.g., bit 0 corresponds to multicast group 0, bit 1 corresponds to multicast group 1, and so on).
Page 439 IDT PCI-to-PCI Bridge Registers Notes MCBLKUTH - Multicast Block Untranslated High (0x354) Field Default Type Description Field Name Value 31:0 MCBLKUT Multicast Block Untranslated. Each bit in this field corresponds to one of the upper 32 multicast groups (e.g., bit 0 corresponds to multicast group 32, bit 1 corresponds to multicast group 33, and so on).
Page 440 IDT PCI-to-PCI Bridge Registers Notes PES12NT12G2 User Manual 20 - 64 July 10, 2013...
Page 441: Proprietary Port Specific Registers
Chapter 21 Proprietary Port Specific Registers ® Port Control Register Notes PORTCTL - Port Control (0x400) Field Default Type Description Field Name Value EWRRPA Enable WRR Port Arbitration. SWSticky When this bit is set, port arbitration selection in the port’s VC Capability structure is ignored and arbitration is done using a weighted round robin (WRR) algorithm controlled with proprietary count registers.
Page 442 IDT Proprietary Port Specific Registers Notes Field Default Type Description Field Name Value FMCC RW1C Failover Mode Change Completed This bit is set in an upstream port whenever failover is enabled in the partition associated with this port (i.e., the FEN bit is set in the corresponding SWPARTxCTL register) and a failover mode change is completed by the corre- sponding failover capability structure (i.e., the FMCC bit in...
Page 443: Port Aer Mask Register
IDT Proprietary Port Specific Registers Notes Field Default Type Description Field Name Value 31:8 Reserved Reserved field. P2PSDATA - PCI-to-PCI Bridge Signal Data (0x410) Field Default Type Description Field Name Value 31:0 SDATA Switch Signal Data. SWSticky This is a general 32-bit read write field that may be used in conjunction with switch signals.
Page 444 IDT Proprietary Port Specific Registers Notes Field Default Type Description Field Name Value CABORT Completer Abort Mask. Sticky When this bit is set, the corresponding bit in the internal, non-software visible PAERSTS register is masked. UECOMP Unexpected Completion Mask. Sticky When this bit is set, the corresponding bit in the internal, non-software visible PAERSTS register is masked.
Page 445: Port Slot Control
IDT Proprietary Port Specific Registers Notes Field Default Type Description Field Name Value Header Log Overflow Mask. Sticky When this bit is set, the corresponding bit in the internal, non-software visible PAERSTS register is masked. 30:21 Reserved Reserved field. Internal Error Mask. Sticky When this bit is set, the corresponding bit in the internal, non-software visible PAERSTS register is masked.
Page 446 IDT Proprietary Port Specific Registers Notes Field Default Type Description Field Name Value PDCE Presence Detected Changed Enable. SWSticky This field contains the initial value of the corresponding field in the PCI Express Slot Control (PCIESCTL) register when the corresponding slot or hot-plug capability is enabled. The intent of this field is to allow the initial value of the cor- responding field in the PCIESCTL register to be controlled following a partition fundamental reset.
Page 447: Internal Error Control And Status Registers
IDT Proprietary Port Specific Registers Notes Field Default Type Description Field Name Value Power Controller Control. SWSticky This field contains the initial value of the corresponding field in the PCI Express Slot Control (PCIESCTL) register when the corresponding slot or hot-plug capability is enabled. The intent of this field is to allow the initial value of the cor- responding field in the PCIESCTL register to be controlled following a partition fundamental reset.
Page 448 IDT Proprietary Port Specific Registers Notes Field Default Type Description Field Name Value IFBCPTLPTO RW1C IFB Completion TLP Time-Out. SWSticky This bit is set when a completion time-out is detected in the IFB. Reserved Reserved field. EFBPTLPTO RW1C EFB Posted TLP Time-Out. SWSticky This bit is set when a posted TLP time-out is detected in the EFB.
Page 449 IDT Proprietary Port Specific Registers Notes Field Default Type Description Field Name Value RBCTLDBE RW1C Replay Buffer Control Double Bit Error. SWSticky This bit is set when a double bit ECC error is detected in the Replay Buffer’s control RAM. DIFBPTLPTO RW1C DMA IFB Posted TLP Time-Out.
Page 450 IDT Proprietary Port Specific Registers Notes Field Default Type Description Field Name Value 30:29 Reserved Reserved field. DE2EPE RW1C DMA End-to-End Data Path Parity Error. SWSticky This bit is set when an end-to-end data path parity error is detected by the DMA. This bit is only applicable for ports that contain a DMA func- tion.
Page 451 IDT Proprietary Port Specific Registers Notes Field Default Type Description Field Name Value P16AER RW1C Port 16 AER Error. SWSticky This bit is at the time that port 16 detects an AER error in one of its functions and the error is not masked by the cor- responding Port AER Mask (PAERMSK) register.
Page 452 IDT Proprietary Port Specific Registers Notes Field Default Type Description Field Name Value EFBCPTLPTO EFB Completion TLP Time-Out. SWSticky This bit controls how an error of the corresponding type is reported. When this bit is set, the error is reported as an uncorrectable internal error.
Page 453 IDT Proprietary Port Specific Registers Notes Field Default Type Description Field Name Value Unreliable Link Detected. SWSticky This bit controls how an error of the corresponding type is reported. When this bit is set, the error is reported as an uncorrectable internal error.
Page 454 IDT Proprietary Port Specific Registers Notes Field Default Type Description Field Name Value DIFBDATDBE DMA IFB Data Double Bit Error. SWSticky This bit controls how an error of the corresponding type is reported. When this bit is set, the error is reported as an uncorrectable internal error.
Page 455 IDT Proprietary Port Specific Registers Notes IERRORSEV1 - Internal Error Reporting Severity 1 (0x490) Field Default Type Description Field Name Value P0AER Port 0 AER Error. SWSticky This bit controls how an error of the corresponding type is reported. When this bit is set, the error is reported as an uncorrectable internal error.
Page 456 IDT Proprietary Port Specific Registers Notes Field Default Type Description Field Name Value P17AER Port 17 AER Error. SWSticky This bit controls how an error of the corresponding type is reported. When this bit is set, the error is reported as an uncorrectable internal error.
Page 457 IDT Proprietary Port Specific Registers Notes Field Default Type Description Field Name Value IFBCTLDBE IFB Control Double Bit Error. This bit always returns a value of zero when read. EFBDATSBE EFB Data Single Bit Error. This bit always returns a value of zero when read. EFBDATDBE EFB Data Double Bit Error.
Page 458 IDT Proprietary Port Specific Registers Notes Field Default Type Description Field Name Value DIFBCTLDBE DMA IFB Control Double Bit Error. This bit always returns a value of zero when read. This bit is only applicable for ports that contain a DMA func- tion.
Page 459 IDT Proprietary Port Specific Registers Notes Field Default Type Description Field Name Value IFBCPTLPTO IFB Completion TLP Time-Out. SWSticky When this bit is set, the corresponding error bit in the IERRORSTS0/1 register is masked from reporting an inter- nal error to the AER Capability Structure of the PCI-to-PCI bridge function.
Page 460 IDT Proprietary Port Specific Registers Notes Field Default Type Description Field Name Value EFBDATSBE EFB Data Single Bit Error. SWSticky When this bit is set, the corresponding error bit in the IERRORSTS0/1 register is masked from reporting an inter- nal error to the AER Capability Structure of the PCI-to-PCI bridge function.
Page 461 IDT Proprietary Port Specific Registers Notes Field Default Type Description Field Name Value DIFBPTLPTO DMA IFB Posted TLP Time-Out. SWSticky When this bit is set, the corresponding error bit in the IERRORSTS0/1 register is masked from reporting an inter- nal error to the AER Capability Structure of the PCI-to-PCI bridge function.
Page 462 IDT Proprietary Port Specific Registers Notes Field Default Type Description Field Name Value DIFBCTLSBE DMA IFB Control Single Bit Error. SWSticky When this bit is set, the corresponding error bit in the IERRORSTS0/1 register is masked from reporting an inter- nal error to the AER Capability Structure of the PCI-to-PCI bridge function.
Page 463 IDT Proprietary Port Specific Registers Notes P2PIERRORMSK1 - PCI-to-PCI Bridge Internal Error Reporting Mask 1 (0x4A4) Field Default Type Description Field Name Value P0AER Port 0 AER Error. SWSticky When this bit is set, the corresponding error bit in the IERRORSTS0/1 register is masked from reporting an inter- nal error to the AER Capability Structure of the PCI-to-PCI bridge function.
Page 464: Physical Layer Control And Status Registers
IDT Proprietary Port Specific Registers Notes Field Default Type Description Field Name Value 15:12 Reserved Reserved field. P16AER Port 16 AER Error. SWSticky When this bit is set, the corresponding error bit in the IERRORSTS0/1 register is masked from reporting an inter- nal error to the AER Capability Structure of the PCI-to-PCI bridge function.
Page 465 IDT Proprietary Port Specific Registers Notes SERDESCFG - SerDes Configuration (0x510) Field Default Type Description Field Name Value RCVD_OVRD Receiver Detect Override. SWSticky Each bit in this register corresponds to a lane associated with this port. Setting this bit causes the lane associated with this bit to indicate that a receiver has been detected on the line.
Page 466 IDT Proprietary Port Specific Registers Notes LANESTS1 - Lane Status 1 (0x520) Field Default Type Description Field Name Value RW1C Receiver Underflow Detected. Sticky Each bit in this field corresponds to a lane associated with the port. A bit is set when the corresponding link receiver is unable to compensate for clock variance between link partners and has inserted one or more zero bytes into the stream.
Page 467 IDT Proprietary Port Specific Registers Notes Field Default Type Description Field Name Value ILSCC Down- Initial Link Speed Change Control. stream This field determines whether a port automatically initiates Switch Port: a speed change to Gen 2 speed, if Gen 2 speed is permis- sible, after initial entry to L0 from Detect.
Page 468 IDT Proprietary Port Specific Registers Notes PHYPRBS - Phy PRBS Seed (0x55C) Field Default Type Description Field Name Value 15:0 SEED 0xFFFF Phy PRBS Seed Value. SWSticky This field contains the PHY PRBS seed value used for crosslink operation. When the value in this register is modified, the PRBS coun- ter associated with this seed is reset to the seed value and re-starts counting.
Page 469: Request Metering
IDT Proprietary Port Specific Registers Notes Field Default Type Description Field Name Value 15:14 Reserved Reserved field TSCTL Timer Start Control. SWSticky Upon rejecting an L1 ASPM entry request from the link part- ner, the switch port counts an amount of time equal to the value in the MTL1ER field before detecting a new request.
Page 470: Wrr Port Arbitration Counts
IDT Proprietary Port Specific Registers Notes Field Default Type Description Field Name Value 31:16 DVADJ Decrement Value Adjustment. SWSticky This field contains the adjustment value used to determine the value by which the request metering counter is decre- mented each 250 MHz clock tick. The value in this field represents a sign-magnitude, fixed- point number with 4 integer bits and 11 fractional bits (i.e., a 1:4:11 format number).
Page 471 IDT Proprietary Port Specific Registers Notes Field Default Type Description Field Name Value 23:16 P2IC Port 2 Initial Count. Description This field contains the initial value of the WRR port arbitra- SWSticky tion count corresponding to port 2. The initial value of this field is 0xFF in Port 2, and 0x0 in all other ports.
Page 472 IDT Proprietary Port Specific Registers Notes VC0PARBCI4 - VC0 Port Arbiter Counter Initialization 4 (0x8A0) Field Default Type Description Field Name Value P16IC Port 16 Initial Count. Description This field contains the initial value of the WRR port arbitra- SWSticky tion count corresponding to port 16.
Page 473: Non-Transparent Multicast Overlay
IDT Proprietary Port Specific Registers Notes Field Default Type Description Field Name Value 15:8 DMA1IC DMA Module 1 Initial Count. Description This field contains the initial value of the WRR port arbitra- SWSticky tion count corresponding to DMA module 1. The initial value of this field is 0xFF in Port 8 (i.e., where DMA module 1 is logically located), and 0x0 in all other ports.
Page 474 IDT Proprietary Port Specific Registers Notes NTMCOVR[3:0]C - NT Multicast Overlay x Configuration Field Default Type Description Field Name Value PART Partition Association. Each bit in this field corresponds to a switch partition (i.e., bit 0 corresponds to partition 0, bit 1 corresponds to parti- tion 1, etc.) When an NT multicast TLP is received on a partition whose corresponding bit is set in this field and a group whose cor-...
Page 475: Aer Error Emulation
IDT Proprietary Port Specific Registers Notes NTMCOVR[3:0]BARL - NT Multicast Overlay x Base Address Low Field Default Type Description Field Name Value OVRSIZE Overlay Size. This field specifies the size in bytes of the overlay aperture as a power of 2. The value in this field must be programmed to six or above.
Page 476 IDT Proprietary Port Specific Registers Notes Field Default Type Description Field Name Value 15:13 Reserved Reserved field. UECOMP Unexpected Completion Trigger. SWSticky Writing a one to this bit causes the corresponding error bit to get set in the PCI-to-PCI Bridge function’s AERUES reg- ister.
Page 477 IDT Proprietary Port Specific Registers Notes Field Default Type Description Field Name Value ADVISORYNF Advisory Non-Fatal Error Trigger. SWSticky If this bit is set together with another error bit in this register for which an advisory non-fatal error is possible (refer to the PCI Express Base Specification), an advisory non-fatal error is logged an reported in the PCI-to-PCI bridge func- tion’s AER capability structure, provided the error severity...
Page 478: Global Address Space Access Registers
IDT Proprietary Port Specific Registers Notes Field Default Type Description Field Name Value Header Log Overflow Trigger. SWSticky Writing a one to this bit causes the corresponding error bit to get set in the PCI-to-PCI Bridge function’s AERCES reg- ister. This bit always returns 0x0 when read. 31:16 Reserved Reserved field.
Page 479 IDT Proprietary Port Specific Registers Notes PES12NT12G2 User Manual 21 - 39 July 10, 2013...
Page 480 IDT Proprietary Port Specific Registers Notes PES12NT12G2 User Manual 21 - 40 July 10, 2013...
Page 481: Nt Endpoint Registers
Chapter 22 NT Endpoint Registers ® Type 0 Configuration Header Registers Notes VID - Vendor Identification (0x000) Field Default Type Description Field Name Value 15:0 0x111D Vendor Identification. This field contains the 16-bit vendor ID value assigned to IDT. See section Vendor ID on page 1-1. DID - Device Identification (0x002) Field Default...
Page 482 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value Bus Master Enable. When this bit is cleared, inter-partition requests are not transmitted by the function. In addition, the function does not issue MSIs. All other requests or completions emitted by this function are not affected by this bit.
Page 483 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value INTS INTx Status. This bit is set when an INTx interrupt is pending from the function. CAPL Capabilities List. This bit is hardwired to one to indicate that this function implements an extended capability list item.
Page 484 IDT NT Endpoint Registers Notes RID - Revision Identification (0x008) Field Default Type Description Field Name Value Revision ID. SWSticky This field contains the revision identification number for the device. See section Revision ID on page 1-1. CCODE - Class Code (0x009) Field Default Type...
Page 485 IDT NT Endpoint Registers Notes BIST - Built-in Self Test Register (0x00F) Field Default Type Description Field Name Value BIST BIST. This value indicates that the function does not implement BIST. BAR0 - Base Address Register 0 (0x010) Field Default Type Description Field...
Page 486 IDT NT Endpoint Registers Notes BAR1 - Base Address Register 1 (0x014) When the MEMSI field in BARSETUP0 is set to memory space (i.e., zero) and the TYPE field is set to 64-bit addressing, BAR1 takes on the function of the upper 32-bits of the BADDR field in BAR0. Otherwise, the BAR format below is used.
Page 487 IDT NT Endpoint Registers Notes BAR2 - Base Address Register 2 (0x018) Field Default Type Description Field Name Value MEMSI Memory Space Indicator. This bit determines if the base address register maps into memory space or I/O space. The value of this field is determined by the MEMSI field in the BARSETUP2 register.
Page 488 IDT NT Endpoint Registers Notes BAR3 - Base Address Register 3 (0x01C) When the MEMSI field in BARSETUP2 is set to memory space (i.e., zero) and the TYPE field is set to 64-bit addressing, BAR3 takes on the function of the upper 32-bits of the BADDR field in BAR2. Otherwise, the BAR format below is used.
Page 489 IDT NT Endpoint Registers Notes BAR4 - Base Address Register 4 (0x020) Field Default Type Description Field Name Value MEMSI Memory Space Indicator. This bit determines if the base address register maps into memory space or I/O space. The value of this field is determined by the MEMSI field in the BARSETUP4 register.
Page 490 IDT NT Endpoint Registers Notes BAR5 - Base Address Register 5 (0x024) When the MEMSI field in BARSETUP4 is set to memory space (i.e., zero) and the TYPE field is set to 64-bit addressing, BAR5 takes on the function of the upper 32-bits of the BADDR field in BAR4. Otherwise, the BAR format below is used.
Page 491 IDT NT Endpoint Registers Notes CCISPTR - CardBus CIS Pointer (0x028) Field Default Type Description Field Name Value 31:0 CCISPTR CardBus CIS Pointer. Not applicable. SUBVID - Subsystem Vendor ID Pointer (0x02C) Field Default Type Description Field Name Value 15:0 SUBVID Subsystem Vendor ID.
Page 492 IDT NT Endpoint Registers Notes INTRLINE - Interrupt Line (0x03C) Field Default Type Description Field Name Value INTRLINE Interrupt Line. This register communicates interrupt line routing informa- tion. Values in this register are programmed by system soft- ware and are system architecture specific. The function does not use the value in this register.
Page 493 IDT NT Endpoint Registers PCI Express Capability Structure Notes PCIECAP - PCI Express Capability (0x040) Field Default Type Description Field Name Value CAPID 0x10 Capability ID. The value of 0x10 identifies this capability as a PCI Express capability structure. 15:8 NXTPTR HWINIT Next Pointer.
Page 494 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value Phantom Functions Supported. This field indicates the support for unclaimed function num- ber to extend the number of outstanding transactions allowed by logically combining unclaimed function numbers with the TLP’s tag identifier. The value is hardwired to 0x0 to indicate that no function number bits are used for phan- tom functions.
Page 495 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value 25:18 CSPLV Captured Slot Power Limit Value. This field in combination with the Slot Power Limit Scale value, specifies the upper limit on power supplied by the slot. Power limit (in Watts) calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field.
Page 496 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value Max Payload Size. This field sets maximum TLP payload size for the function. As a receiver, the function must handle TLPs as large as the set value. As a transmitter, the function must not gener- ate TLPs exceeding the set value.
Page 497 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value 14:12 MRRS Maximum Read Request Size. The NT function passes transactions through the NTB with the size unmodified. Therefore, this field has no functional effect on the behavior of the NTB. The user must ensure that no translated TLPs emitted by this NT function exceed the value programmed in this field (i.e., TLPs received by an NT function in another partition...
Page 498 IDT NT Endpoint Registers Notes PCIELCAP - PCI Express Link Capabilities (0x04C) Field Default Type Description Field Name Value MAXLNKSPD Maximum Link Speed. SWSticky This field indicates the supported link speeds of the port. 1 - (gen1) 2.5 GT/s 2 - (gen2) 5 GT/s others - reserved Note: This device advertises support for 5 GT/s regard- less of the setting of this field.
Page 499 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value 17:15 L1EL L1 Exit Latency. SWSticky This field indicates the L1 exit latency for the given PCI Express link. Transitioning from L1 to L0 always requires approximately 2.3 uS. Therefore, a value 2 µs to less than 4 µs is reported with a default value of 0x2.
Page 500 IDT NT Endpoint Registers Notes PCIELCTL - PCI Express Link Control (0x050) Field Default Type Description Field Name Value ASPM Active State Power Management (ASPM) Control. This field controls the level of ASPM supported by the link. The initial value corresponds to disabled. 0x0 - (disabled) disabled 0x1 - (l0s) L0s enable entry 0x2 - (l1) L1 enable entry...
Page 501 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value CCLK Common Clock Configuration. When set, this bit indicates that this port and the port at the opposite end of the link are operating with a distributed common reference clock. When a port operates in a multi-function mode, software must set this bit identically for all functions of the port.
Page 502 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value HWINIT Negotiated Link Width. This field indicates the negotiated width of the link. 00 0001b - x1 00 0010b - x2 00 0100b - x4 00 1000b - x8 00 1100b - x12 01 0000b - x16 10 0000b - x32...
Page 503 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value CTDS Completion Timeout Disable Supported. The default value indicates support for completion timeout disable. ARIFS ARI Forwarding Supported. Not applicable. ATOPRS AtomicOp Routing Supported. Not applicable. ATOPC32S 32-bit AtomicOp Completer Supported. Not supported.
Page 504 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value Completion Timeout Disable. The NT function does not track non-posted requests that it transmits (i.e., requests that crossed the NTB). As a result, the NT function does not implement a completion timeout mechanism.
Page 505 IDT NT Endpoint Registers Notes PCIELCTL2 - PCI Express Link Control 2 (0x070) Field Default Type Description Field Name Value If NT If NT func- Target Link Speed. func- tion is func- This field is only applicable for port operating modes in tion is tion 0 of the which the NT function is function 0 of the port.
Page 506 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value If NT Transmit Margin. func- Sticky This field is only applicable for port operating modes in tion is which the NT function is function 0 of the port. func- When applicable: tion 0...
Page 507 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value CSOS If NT Compliance SOS. func- Sticky This field is only applicable for port operating modes in tion is which the NT function is function 0 of the port. func- When applicable: tion 0...
Page 508: Pci Power Management Capability Structure
IDT NT Endpoint Registers PCI Power Management Capability Structure Notes PMCAP - PCI Power Management Capabilities (0x0C0) Field Default Type Description Field Name Value CAPID Capability ID. The value of 0x1 identifies this capability as a PCI power management capability structure. 15:8 NXTPTR HWINIT...
Page 509: Message Signaled Interrupt Capability Structure
IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value NOSOFTRST No Soft Reset. SWSticky This bit indicates if the configuration context is preserved by the function when the device transitions from a D3hot to D0 power management state. 0x0 - (reset) State reset 0x1 - (preserved) State preserved Reserved...
Page 510 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value Enable. This bit enables MSI. 0x0 - (disable) disabled 0x1 - (enable) enabled 19:17 Multiple Message Capable. This field contains the number of requested messages. 22:20 Multiple Message Enable. Hardwired to one message.
Page 511: Subsystem Id And Subsystem Vendor Id
IDT NT Endpoint Registers Subsystem ID and Subsystem Vendor ID Notes SSIDSSVIDCAP - Subsystem ID and Subsystem Vendor ID Capability (0x0F0) Field Default Type Description Field Name Value CAPID Capability ID. The value of 0xD identifies this capability as a SSID/SSVID capability structure.
Page 512 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value Register Number. This field selects the configuration register number as defined by Section 7.2.2 of the PCI Express Base Specifi- cation, Rev. 2.1. The following restrictions apply when programming this reg- ister: 1) The value of this register must not be programmed to point to the address offset of this register (i.e., 0xF8) or the...
Page 513 IDT NT Endpoint Registers Advanced Error Reporting (AER) Extended Capability Notes AERCAP - AER Capabilities (0x100) Field Default Type Description Field Name Value 15:0 CAPID Capability ID. The value of 0x1 indicates an Advanced Error Reporting capability structure. 19:16 CAPVER Capability Version.
Page 514 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value RCVOVR RW1C Receiver Overflow Status. Sticky This bit is set when a receiver overflow is detected. MALFORMED RW1C Malformed TLP Status. Sticky This bit is set when a malformed TLP is detected. ECRC RW1C ECRC Status.
Page 515 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value DLPERR Data Link Protocol Error Mask. Sticky When this bit is set, the corresponding bit in the AERUES register is masked. When a bit is masked in the AERUES register, the corresponding event is not logged in the AER Header Log registers, the First Error Pointer field (FEPTR) in the AERCTL register is not updated, and an error is not...
Page 516 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value MALFORMED Malformed TLP Mask. Sticky When this bit is set, the corresponding bit in the AERUES register is masked. When a bit is masked in the AERUES register, the corresponding event is not logged in the AER Header Log registers, the First Error Pointer field (FEPTR) in the AERCTL register is not updated, and an error is not reported to the root complex.
Page 517 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value Uncorrectable Internal Error Mask. Sticky When this bit is set, the corresponding bit in the AERUES register is masked. When a bit is masked in the AERUES register, the corresponding event is not logged in the advanced capability structure, the First Error Pointer field (FEPTR) in the AERCTL register is not updated, and an error is not reported to the root complex.
Page 518 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value COMPTO Completion Timeout Severity. Sticky This function does not track non-posted requests it trans- mits (i.e., requests that crossed the NTB). Therefore, this bit has no effect when set. CABORT Completer Abort Severity.
Page 519 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value TLPPBE TLP Prefix Blocked Error Severity. Not applicable. 31:26 Reserved Reserved field. AERCES - AER Correctable Error Status (0x110) Field Default Type Description Field Name Value RCVERR RW1C Receiver Error Status.
Page 520 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value RW1C Header Log Overflow Status. Sticky This bit is set when an error that requires packet-header logging occurs but the packet header cannot be logged by the function’s AER Header Log registers (AERHL[1:4]DW). A packet’s header cannot be logged in the AER Header Log registers when an error occurs while the First Error Pointer (FEPTR field in the AERCTL register) is valid.
Page 521 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value RPLYROVR Replay Number Rollover Mask. Sticky When this bit is set, the corresponding bit in the AERCES register is masked. When a bit is masked in the AERCES register, the corresponding event is not reported to the root complex.
Page 522 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value Header Log Overflow Mask. Sticky When this bit is set, the corresponding bit in the AERCES register is masked. When a bit is masked in the AERCES register, the corresponding event is not reported to the root complex.
Page 523: Device Serial Number Extended Capability
IDT NT Endpoint Registers Notes AERHL1DW - AER Header Log 1st Doubleword (0x11C) Field Default Type Description Field Name Value 31:0 Header Log. Sticky This field contains the 1st doubleword of the TLP header that resulted in the first reported uncorrectable error. AERHL2DW - AER Header Log 2nd Doubleword (0x120) Field Default...
Page 524: Pci Express Virtual Channel Capability
IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value 31:20 NXTPTR HWINIT Next Pointer. (See This field contains a pointer to the next capability structure. description) The default value of this register depends on the port’s MSWSticky operating mode.
Page 525 IDT NT Endpoint Registers Notes PCIEVCECAP - PCI Express VC Extended Capability Header (0x200) Field Default Type Description Field Name Value 15:0 CAPID Capability ID. The value of 0x2 indicates a Virtual Channel Capability Structure. 19:16 CAPVER Capability Version. The value of 0x1 indicates compatibility with the PCI Express Base specification, Rev 2.1.
Page 526 IDT NT Endpoint Registers Notes PVCCAP2- Port VC Capability 2 (0x208) Field Default Type Description Field Name Value VCARBCAP VC Arbitration Capability. Not applicable (only the default VC0 is implemented). 23:8 Reserved Reserved field. 31:24 VCATBLOFF VC Arbitration Table Offset. Not applicable.
Page 527 IDT NT Endpoint Registers Notes VCR0CTL- VC Resource 0 Control (0x214) Field Default Type Description Field Name Value TCVCMAP bit 0: 0xFF TC/VC Map. This field indicates the TCs that are mapped to the VC resource. bits 1 Each bit corresponds to a TC. When a bit is set, the corre- through sponding TC is mapped to the VC.
Page 528 IDT NT Endpoint Registers ACS Extended Capability Notes ACSECAPH - ACS Extended Capability Header (0x320) Field Default Type Description Field Name Value 15:0 CAPID Capability ID. The value of 0xD indicates an ACS extended capability structure. 19:16 CAPVER Capability Version. The value of 0x1 indicates compatibility with the PCI Express Base Specification.
Page 529 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value ACS P2P Egress Control. The switch does not support ACS P2P Egress Control among functions in a multi-function upstream port. ACS Direct Translated P2P. SWSticky If set, indicates that this function implements ACS Direct Translated Peer-to-Peer.
Page 530: Multicast Extended Capability
IDT NT Endpoint Registers Multicast Extended Capability Notes MCCAPH - Multicast Extended Capability Header (0x330) Field Default Type Description Field Name Value 15:0 CAPID 0x12 Capability ID. The value of 0x12 indicates a multicast capability structure. 19:16 CAPVER Capability Version. The value of 0x1 indicates compatibility with the PCI Express Base Specification.
Page 531 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value Multicast Enable. When this bit is set, multicast is enabled in the switch parti- tion associated with this function. This field must be set identically in all port functions in the partition associated with this port.
Page 532 IDT NT Endpoint Registers Notes MCRCVL- Multicast Receive Low (0x340) Field Default Type Description Field Name Value MCRCV Multicast Receive. Each bit in this field corresponds to one of the lower 32 mul- ticast groups (e.g., bit 0 corresponds to multicast group 0, bit 1 corresponds to multicast group 1, and so on).
Page 533: Nt Registers
IDT NT Endpoint Registers Notes MCBLKUTL- Multicast Block Untranslated Low (0x350) Field Default Type Description Field Name Value 31:0 MCBLKUT Multicast Block Untranslated. Not applicable (the NT function does not implement Address Translation Services (ATS)). MCBLKUTH - Multicast Block Untranslated High (0x354) Field Default Type...
Page 534: Nt Interrupt And Signaling
IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value Address Type Processing. SWSticky When the IDPROTDIS bit in this register is set, this bit con- trols Address Type processing on posted request TLPs received by the NT endpoint. Address Type processing is described in section Address Type Processing on page 14- When the IDPROTDIS bit in this register is cleared, this bit has no effect.
Page 535 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value Reserved Reserved field. TMPSENSOR RW1C Temperature Sensor Alarm. This bit is set when a temperature sensor alarm is triggered (i.e., one of the temperature threshold bits in the TMPSTS register transitions from 0x0 to 0x1, and the corresponding bit is enabled in the TMPCTL register).
Page 536: Internal Error Reporting Masks
IDT NT Endpoint Registers Notes NTGSIGNAL - NT Endpoint Global Signal (0x410) Field Default Type Description Field Name Value GSIGNAL Global Signal Writing a one to a bit in this field generates a switch signal to the partition associated with this NT function. This results in the bit corresponding to the partition being set in the Global Signal (GSIGNAL) field in the Switch Event Global Signal Status (SEGSIGSTS) register.
Page 537 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value EFBCPTLPTO EFB Completion TLP Time-Out SWSticky When this bit is set, the corresponding error bit in the IERRORSTS0/1 register is masked from reporting an inter- nal error to the AER Capability Structure of the NT function. This bit does not affect the state of the corresponding bit in the IERRORSTS0/1 register.
Page 538 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value EFBCTLDBE EFB Control Double Bit Error SWSticky When this bit is set, the corresponding error bit in the IERRORSTS0/1 register is masked from reporting an inter- nal error to the AER Capability Structure of the NT function. This bit does not affect the state of the corresponding bit in the IERRORSTS0/1 register.
Page 539 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value DIFBCPTLPTO DMA IFB Completion TLP Time-Out SWSticky When this bit is set, the corresponding error bit in the IERRORSTS0/1 register is masked from reporting an inter- nal error to the AER Capability Structure of the NT function. This bit does not affect the state of the corresponding bit in the IERRORSTS0/1 register.
Page 540 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value DEFBDATSBE DMA EFB Data Single Bit Error SWSticky When this bit is set, the corresponding error bit in the IERRORSTS0/1 register is masked from reporting an inter- nal error to the AER Capability Structure of the NT function. This bit does not affect the state of the corresponding bit in the IERRORSTS0/1 register.
Page 541 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value P2AER Port 2 AER Error SWSticky When this bit is set, the corresponding error bit in the IERRORSTS0/1 register is masked from reporting an inter- nal error to the AER Capability Structure of the NT function. This bit does not affect the state of the corresponding bit in the IERRORSTS0/1 register.
Page 542: Doorbell Registers
IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value P18AER Port 18 AER Error SWSticky When this bit is set, the corresponding error bit in the IERRORSTS0/1 register is masked from reporting an inter- nal error to the AER Capability Structure of the NT function. This bit does not affect the state of the corresponding bit in the IERRORSTS0/1 register.
Page 543: Message Registers
IDT NT Endpoint Registers Notes INDBELLMSK - NT Inbound Doorbell Mask (0x42C) Field Default Type Description Field Name Value 31:0 INDBELLMSK Inbound Doorbell Mask. Each bit in this field corresponds to one of the 32 inbound doorbells associated with the NT endpoint. When a bit in this field is set, the corresponding bit in the NT inbound doorbell status register is masked from generating an NT interrupt.
Page 544 IDT NT Endpoint Registers Notes MSGSTS - Message Status (0x460) Field Default Type Description Field Name Value OUTMSGSTS0 RW1C Outbound Message 0 Status. This bit is set when a write to the OUTMSG0 register fails. See section Message Registers on page 14-17 for a description of the message registers.
Page 545: Bar Configuration
IDT NT Endpoint Registers Notes MSGSTSMSK - Message Status Mask (0x464) Field Default Type Description Field Name Value OUTMSGSTS0 Outbound Message 0 Mask. When this bit is set, assertion of the corresponding bit in the MSGSTS register is masked from generating an interrupt. OUTMSGSTS1 Outbound Message 1 Mask.
Page 546 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value TYPE Address Select. SWSticky This field determines the value reported in the TYPE field of the corresponding BAR and selects the address space decoding used when memory space is selected in the MEMSI field in this register.
Page 547 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value 12:11 ATRAN Address Translation. When the BAR is configured to operate as an address win- dow, this field specifies the type of address translation that is used. This field is read-only with a value of zero since BAR 0 only supports direct address translation.
Page 548 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value 31:2 TADDR Translated Base Address. SWSticky When the BAR is configured for direct address translation, this field specifies the translated base address. The translated base address is 64-bits. This field contains bits 2 through 31 of the translated base address.
Page 549 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value TYPE Address Select. SWSticky This field determines the value reported in the TYPE field of the corresponding BAR and selects the address space decoding used when memory space is selected in the MEMSI field in this register.
Page 550 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value SIZE Address Space Size. SWSticky This field selects the size, in address bits, of the address space for the corresponding BAR. When the MEMSI field in BARSETUP0 is set to memory space (i.e., zero) and the TYPE field is set to 64-bit addressing, BAR1 takes on the function of the upper 32-bits of the BADDR field in BAR0.
Page 551 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value BAR Enable. SWSticky When cleared, the corresponding BAR is disabled and returns a zero when read (i.e., configuration values in this register are ignored and all fields of the BAR take on a value of zero).
Page 552 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value 31:2 TADDR Translated Base Address. SWSticky When the BAR is configured for direct address translation, this field specifies the translated base address. The translated base address is 64-bits. This field contains bits 2 through 31 of the translated base address.
Page 553 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value PREF Prefetchable Select. SWSticky This field determines the value reported in the PREF field of the corresponding BAR. 0x0 - (nonprefetch) non-prefetchable. 0x1 - (prefetch) prefetchable. SIZE Address Space Size. SWSticky This field selects the size, in address bits, of the address space for the corresponding BAR or BAR pair when 64-bit...
Page 554 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value 15:13 TPART Translated Partition. SWSticky When the BAR is configured to operate as an address win- dow with direct address translation, this field specifies the translated partition number. 30:16 Reserved Reserved field.
Page 555 IDT NT Endpoint Registers Notes BARUTBASE2 - BAR 2 Upper Translated Base Address (0x49C) Field Default Type Description Field Name Value 31:0 TADDR Translated Base Address. SWSticky When the BAR is configured for direct address translation, this field specifies the translated base address. The translated base address is 64-bits.
Page 556 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value SIZE Address Space Size. SWSticky This field selects the size, in address bits, of the address space for the corresponding BAR. When the MEMSI field in BARSETUP2 is set to memory space (i.e., zero) and the TYPE field is set to 64-bit addressing, BAR3 takes on the function of the upper 32-bits of the BADDR field in BAR2.
Page 557 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value BAR Enable. SWSticky When cleared, the corresponding BAR is disabled and returns a zero when read (i.e., configuration values in this register are ignored and all fields of the BAR take on a value of zero).
Page 558 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value 31:2 TADDR Translated Base Address. SWSticky When the BAR is configured for direct address translation, this field specifies the translated base address. The translated base address is 64-bits. This field contains bits 2 through 31 of the translated base address.
Page 559 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value SIZE Address Space Size. SWSticky This field selects the size, in address bits, of the address space for the corresponding BAR or BAR pair when 64-bit addressing is selected. Assuming the size field is set to a valid value, the size of the address space requested by the BADDR field in the corre- SIZE...
Page 560 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value BAR Enable. SWSticky When cleared, the corresponding BAR is disabled and returns a zero when read (i.e., configuration values in this register are ignored and all fields of the BAR take on a value of zero).
Page 561 IDT NT Endpoint Registers Notes BARUTBASE4 - BAR 4 Upper Translated Base Address (0x4BC) Field Default Type Description Field Name Value 31:0 TADDR Translated Base Address. SWSticky When the BAR is configured for direct address translation, this field specifies the translated base address. The translated base address is 64-bits.
Page 562 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value PREF Prefetchable Select. SWSticky This field determines the value reported in the PREF field of the corresponding BAR. When the MEMSI field in BARSETUP4 is set to memory space (i.e., zero) and the TYPE field is set to 64-bit addressing, BAR5 takes on the function of the upper 32-bits of the BADDR field in BAR4.
Page 563 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value 12:11 ATRAN Address Translation. When the BAR is configured to operate as an address win- dow, this field specifies the type of address translation that is used. This field is read-only with a value of zero since BAR 5 only supports direct address translation.
Page 564: Mapping Table
IDT NT Endpoint Registers Notes BARLTBASE5 - BAR 5 Lower Translated Base Address (0x4C8) Field Default Type Description Field Name Value Reserved Reserved field. 31:2 TADDR Translated Base Address. SWSticky When the BAR is configured for direct address translation, this field specifies the translated base address. The translated base address is 64-bits.
Page 565 IDT NT Endpoint Registers Notes NTMTBLSTS - NT Mapping Table Status (0x4D4) Field Default Type Description Field Name Value RW1C NT Mapping Table Access Error Sticky This bit is set if an invalid partition NT Mapping Table entry is accessed or when an NT Mapping Table protection viola- tion occurs.
Page 566 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value 19:17 PART Partition SWSticky Reading this field returns the PART field of the NT Mapping table entry specified by the partition NT Mapping table address in the NTMTBLADDR register. Writing to this field updates the PART field of the NT Mapping table entry spec- ified by the partition NT Mapping table address.
Page 567: Lookup Table
IDT NT Endpoint Registers Lookup Table Notes LUTOFFSET - Lookup Table Offset (0x4E0) Field Default Type Description Field Name Value INDEX Lookup Table Index. SWSticky This field selects the index of the lookup table accessed when the lookup table data registers (i.e., LUTLDATA, LUT- MDATA and LUTUDATA) are read or written.
Page 568: Aer Error Emulation
IDT NT Endpoint Registers Notes LUTMDATA - Lookup Table Middle Data (0x4E8) Field Default Type Description Field Name Value 31:0 TADDR Translated Base Address. SWSticky This field contains bits 63 through 32 of the translated base address field associated with the lookup table entry selected by the BAR and INDEX fields of the Lookup Table Offset (LUTOFFSET) register.
Page 569 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value 11:5 Reserved Reserved field. POISONED Poisoned TLP Trigger. SWSticky Writing a one to this bit causes the corresponding error bit to get set in the AERUES register. This bit always returns 0x0 when read.
Page 570 IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value ADVISORYNF Advisory Non-Fatal Error Trigger. SWSticky If this bit is set together with another error bit in this register for which an advisory non-fatal error is possible (refer to the PCI Express Base Specification), an advisory non-fatal error is logged an reported in the NT function’s AER capa- bility structure, provided the error severity for the selected...
Page 571: Punch-Through Configuration Registers
IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value Header Log Overflow Trigger. SWSticky Writing a one to this bit causes the corresponding error bit to get set in the AERCES register. This bit always returns 0x0 when read. 31:16 Reserved Reserved field.
Page 572 IDT NT Endpoint Registers Notes PTCCTL1 - Punch-Through Configuration Control 1 (0x514) Field Default Type Description Field Name Value CFGTYPE Configuration Access Type This field selects the type of configuration access gener- ated using the punch-through mechanism. 0x0 - (type0) type 0 configuration access 0x1 - (type1) type 1 configuration access Operation This field selects the type of configuration operation to be...
Page 573: Nt Multicast
IDT NT Endpoint Registers Notes Field Default Type Description Field Name Value DONE RW1C Punch-Through Configuration Transaction Completed. This bit is set when a punch-through configuration transac- tion has completed and the STATUS field is valid. Writing a one to this bit clears the status bit or aborts a punch- through operation in progress.
Page 574 IDT NT Endpoint Registers Global Address Space Access Registers Notes GASAADDR - Global Address Space Access Address (0xFF8) Field Default Type Description Field Name Value Reserved Reserved field. 18:2 GADDR Global Address. This field selects the system address of the register to be accessed via the GASADATA register.
Page 575: Dma Function Registers
Chapter 23 DMA Function Registers ® Type 0 Configuration Header Registers Notes VID - Vendor Identification (0x000) Field Default Type Description Field Name Value 15:0 0x111D Vendor Identification. This field contains the 16-bit vendor ID value assigned to IDT. See section Vendor ID on page 1-1. DID - Device Identification (0x002) Field Default...
Page 576 IDT DMA Function Registers Notes Field Default Type Description Field Name Value Bus Master Enable. When this bit is set, the DMA function is allowed to issue memory requests. When this bit is cleared, the DMA func- tion does not transmit memory requests. Note that the DMA function never issues I/O requests.
Page 577 IDT DMA Function Registers Notes PCISTS - PCI Status (0x006) Field Default Type Description Field Name Value Reserved Reserved field. INTS INTx Status. This bit is set when an INTx interrupt is pending from the function. CAPL Capabilities List. This bit is hardwired to one to indicate that this function implements an extended capability list item.
Page 578 IDT DMA Function Registers Notes Field Default Type Description Field Name Value RW1C Detected Parity Error. This bit is set by the function whenever it receives a poi- soned TLP regardless of the state of the PERRE bit in the PCI Command register.
Page 579 IDT DMA Function Registers Notes HDR - Header Type (0x00E) Field Default Type Description Field Name Value 0x80 Header Type. This field indicates the configuration space header type for the DMA function (type 0 header). Since the DMA function always co-exists with another func- tion in the port, this field has a value of 0x80.
Page 580 IDT DMA Function Registers Notes Field Default Type Description Field Name Value 31:12 BADDR Base Address. This field specifies the address bits to be used by the func- tion in decoding and accepting transactions. The BAR aperture for this BAR is always 4 KB (i.e., bits [11:4] in this register are hardwired to 0x0).
Page 581 IDT DMA Function Registers Notes BAR5 - Base Address Register 5 (0x024) Field Default Type Description Field Name Value 31:0 Reserved Not supported. CCISPTR - CardBus CIS Pointer (0x028) Field Default Type Description Field Name Value 31:0 CCISPTR CardBus CIS Pointer. Not applicable.
Page 582 IDT DMA Function Registers Notes CAPPTR - Capabilities Pointer (0x034) Field Default Type Description Field Name Value CAPPTR 0x40 Capabilities Pointer. SWSticky This field specifies a pointer to the head of the capabilities structure. INTRLINE - Interrupt Line (0x03C) Field Default Type Description...
Page 583: Pci Express Capability Structure
IDT DMA Function Registers Notes MAXLAT - Maximum Latency (0x03F) Field Default Type Description Field Name Value MAXLAT Maximum Latency. Not applicable. PCI Express Capability Structure PCIECAP - PCI Express Capability (0x040) Field Default Type Description Field Name Value CAPID 0x10 Capability ID.
Page 584 IDT DMA Function Registers Notes PCIEDCAP - PCI Express Device Capabilities (0x044) Field Default Type Description Field Name Value MPAYLOAD HWINIT Maximum Payload Size Supported. (See This field indicates the maximum payload size that the description) device can support for TLPs. MSWSticky The default value of this field is automatically set by the hardware based on the port’s maximum link width as deter-...
Page 585 IDT DMA Function Registers Notes Field Default Type Description Field Name Value Power Indicator Present. In PCI Express 1.0a when set, this bit indicates that a Power Indicator is implemented on the card/module. The value of this field is undefined in the PCI Express Base Specification Rev.
Page 586 IDT DMA Function Registers Notes Field Default Type Description Field Name Value URREN Unsupported Request Reporting Enable. This bit controls reporting of unsupported requests by this function. Enable Relaxed Ordering. When this bit is set, the DMA function is permitted to set the relaxed-ordering bit in the attributes field of the transactions it initiates (refer to section TLP Attribute and Traffic Class Control on page 15-20).
Page 587 IDT DMA Function Registers Notes Field Default Type Description Field Name Value Enable No Snoop. When this bit is set, the DMA function is permitted to set the No Snoop bit in the attributes field of the transactions it initi- ates (refer to section TLP Attribute and Traffic Class Control on page 15-20).
Page 588 IDT DMA Function Registers Notes Field Default Type Description Field Name Value Transactions Pending. This bit is set when the DMA function has issued non- posted requests that have not been completed. This bit is cleared when all outstanding non-posted requests have been completed or terminated via the completion timeout mechanism.
Page 589 IDT DMA Function Registers Notes Field Default Type Description Field Name Value 11:10 ASPMS Active State Power Management (ASPM) Support. SWSticky This default value of this field is 0x3 to indicate that L0s and L1 are supported. This field may be overridden to allow user control over the ASPM capabilities of this port (L0s and/or L1).
Page 590 IDT DMA Function Registers Notes PCIELCTL - PCI Express Link Control (0x050) Field Default Type Description Field Name Value ASPM Active State Power Management (ASPM) Control. This field controls the level of ASPM supported by the link. The initial value corresponds to disabled. 0x0 - (disabled) disabled 0x1 - (l0s) L0s enable entry 0x2 - (l1) L1 enable entry...
Page 591 IDT DMA Function Registers Notes Field Default Type Description Field Name Value HAWD Hardware Autonomous Width Disable. Not applicable. LBWINTEN Link Bandwidth Management Interrupt Enable. Not applicable. LABWINTEN Link Autonomous Bandwidth Interrupt Enable. Not applicable. 15:12 Reserved Reserved field. PCIELSTS - PCI Express Link Status (0x052) Field Default Type...
Page 592 IDT DMA Function Registers Notes Field Default Type Description Field Name Value DLLLA Data Link Layer Link Active. Not applicable. LBWSTS Link Bandwidth Management Status. Not applicable. LABWSTS Link Autonomous Bandwidth Status. Not applicable. PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064) Field Default Type...
Page 593 IDT DMA Function Registers Notes Field Default Type Description Field Name Value EFMTFS Extended Fmt Field Supported. The switch does not support the 3-bit definition of the FMT field in TLPs. E2ETPS End-to-End TLP Prefix Supported. The switch does not support End-to-End TLP Prefixes. 31:22 Reserved Reserved field.
Page 594 IDT DMA Function Registers Notes Field Default Type Description Field Name Value IDOCE IDO Completion Enable. Not supported. LTRME LTR Mechanism Enable. Not supported. 14:11 Reserved Reserved field. E2ETLPPB End-to-End TLP Prefix Blocking. Not supported. PCIEDSTS2 - PCI Express Device Status 2 (0x06A) Field Default Type...
Page 595: Pci Power Management Capability Structure
IDT DMA Function Registers Notes Field Default Type Description Field Name Value CSOS Compliance SOS. Not applicable (function 0 of the port controls this function- ality). Compliance De-emphasis. Not applicable (function 0 of the port controls this function- ality). 15:13 Reserved Reserved field.
Page 596 IDT DMA Function Registers Notes Field Default Type Description Field Name Value Reserved Reserved field. DEVSP Device Specific Initialization. SWSticky The value of zero indicates that no device specific initializa- tion is required. 24:22 AUXI AUX Current. The switch does not use auxiliary current. D1 Support.
Page 597: Message Signaled Interrupt Capability Structure
IDT DMA Function Registers Notes Field Default Type Description Field Name Value 21:16 Reserved Reserved field. B2B3 B2/B3 Support. Does not apply to PCI Express. BPCCE Bus Power/Clock Control Enable. Does not apply to PCI Express. 31:24 DATA Data. This optional field is not implemented. Message Signaled Interrupt Capability Structure MSICAP - Message Signaled Interrupt Capability and Control (0x0D0) Field...
Page 598: Extended Configuration Space Access Registers
IDT DMA Function Registers Notes MSIADDR - Message Signaled Interrupt Address (0x0D4) Field Default Type Description Field Name Value Reserved Reserved field. 31:2 ADDR Message Address. This field specifies the lower portion of the DWORD address of the MSI memory write transaction. Refer to section Interrupts on page 15-24 for restrictions on the programming of this field.
Page 599 IDT DMA Function Registers Notes Field Default Type Description Field Name Value Register Number. This field selects the configuration register number as defined by Section 7.2.2 of the PCI Express Base Specifi- cation Rev. 2.1. The value of this register must not be programmed to point to the address offset of this register (i.e., 0xF8) or the ECF- GDATA register (i.e., 0xFC).
Page 600 IDT DMA Function Registers Advanced Error Reporting (AER) Extended Capability Notes AERCAP - AER Capabilities (0x100) Field Default Type Description Field Name Value 15:0 CAPID Capability ID. The value of 0x1 indicates an Advanced Error Reporting capability structure. 19:16 CAPVER Capability Version.
Page 601 IDT DMA Function Registers Notes Field Default Type Description Field Name Value RCVOVR RW1C Receiver Overflow Status. Sticky This bit is set when a receiver overflow is detected. MALFORMED RW1C Malformed TLP Status. Sticky This bit is set when a malformed TLP is detected. ECRC RW1C ECRC Status.
Page 602 IDT DMA Function Registers Notes Field Default Type Description Field Name Value DLPERR Data Link Protocol Error Mask. Sticky When this bit is set, the corresponding bit in the AERUES register is masked. When a bit is masked in the AERUES register, the corresponding event is not logged in the AER Header Log registers, the First Error Pointer field (FEPTR) in the AERCTL register is not updated, and an error is not...
Page 603 IDT DMA Function Registers Notes Field Default Type Description Field Name Value RCVOVR Receiver Overflow Mask. Sticky When this bit is set, the corresponding bit in the AERUES register is masked. When a bit is masked in the AERUES register, the corresponding event is not logged in the AER Header Log registers, the First Error Pointer field (FEPTR) in the AERCTL register is not updated, and an error is not reported to the root complex.
Page 604 IDT DMA Function Registers Notes Field Default Type Description Field Name Value Uncorrectable Internal Error Mask. Sticky When this bit is set, the corresponding bit in the AERUES register is masked. When a bit is masked in the AERUES register, the corresponding event is not logged in the advanced capability structure, the First Error Pointer field (FEPTR) in the AERCTL register is not updated, and an error is not reported to the root complex.
Page 605 IDT DMA Function Registers Notes Field Default Type Description Field Name Value COMPTO Completion Timeout Severity. Sticky This bit controls the severity of the reported error. If this bit is set, the event is reported as a fatal error. When this bit is cleared, the event is reported as an uncorrectable error.
Page 606 IDT DMA Function Registers Notes Field Default Type Description Field Name Value TLPPBE TLP Prefix Blocked Error Status. Not applicable. 31:26 Reserved Reserved field. AERCES - AER Correctable Error Status (0x110) Field Default Type Description Field Name Value RCVERR RW1C Receiver Error Status.
Page 607 IDT DMA Function Registers Notes Field Default Type Description Field Name Value RW1C Header Log Overflow Status. Sticky This bit is set when an error that requires packet-header logging occurs but the packet header cannot be logged by the function’s AER Header Log registers (AERHL[1:4]DW). A packet’s header cannot be logged in the AER Header Log registers when an error occurs while the First Error Pointer (FEPTR field in the AERCTL register) is valid.
Page 608 IDT DMA Function Registers Notes Field Default Type Description Field Name Value RPLYROVR Replay Number Rollover Mask. Sticky When this bit is set, the corresponding bit in the AERCES register is masked. When a bit is masked in the AERCES register, the corresponding event is not reported to the root complex.
Page 609 IDT DMA Function Registers Notes Field Default Type Description Field Name Value Header Log Overflow Mask. Sticky When this bit is set, the corresponding bit in the AERCES register is masked. When a bit is masked in the AERCES register, the corresponding event is not reported to the root complex.
Page 610: Acs Extended Capability
IDT DMA Function Registers Notes AERHL1DW - AER Header Log 1st Doubleword (0x11C) Field Default Type Description Field Name Value 31:0 Header Log. Sticky This field contains the 1st doubleword of the TLP header that resulted in the first reported uncorrectable error. AERHL2DW - AER Header Log 2nd Doubleword (0x120) Field Default...
Page 611 IDT DMA Function Registers Notes Field Default Type Description Field Name Value 31:20 NXTPTR HWINIT Next Pointer. (See This field contains a pointer to the next capability structure. description) The default value of this register depends on the port’s MSWSticky operating mode.
Page 612: Dma Registers
IDT DMA Function Registers Notes Field Default Type Description Field Name Value ACS Translation Blocking Enable. Not applicable to multi-function upstream ports. ACS P2P Request Redirect Enable. When set, this function performs ACS Peer-to-Peer Request Redirect for function-to-function transfers. Note: This field becomes read-only-zero when the corre- sponding bit in the ACSCAP register is cleared.
Page 613: Dma Aer Error Emulation
IDT DMA Function Registers Notes Field Default Type Description Field Name Value PREF Prefetchable Select. SWSticky This field determines the value reported in the PREF field of the corresponding BAR. 0x0 - (nonprefetch) non-prefetchable. 0x1 - (prefetch) prefetchable. 30:4 Reserved Reserved field.
Page 614 IDT DMA Function Registers Notes Field Default Type Description Field Name Value ECRC ECRC Trigger. SWSticky Writing a one to this bit causes the corresponding error bit to get set in the PCI-to-PCI Bridge function’s AERUES reg- ister. This bit always returns 0x0 when read. UR Trigger.
Page 615: Internal Error Reporting Masks
IDT DMA Function Registers Notes Field Default Type Description Field Name Value RPLYROVR Replay Number Rollover Trigger. SWSticky Writing a one to this bit causes the corresponding error bit to get set in the PCI-to-PCI Bridge function’s AERCES reg- ister. This bit always returns 0x0 when read. 11:9 Reserved Reserved field.
Page 616 IDT DMA Function Registers Notes Field Default Type Description Field Name Value EFBPTLPTO EFB Posted TLP Time-Out. SWSticky When this bit is set, the corresponding error bit in the IERRORSTS0/1 register is masked from reporting an inter- nal error to the AER Capability Structure of the DMA func- tion.
Page 617 IDT DMA Function Registers Notes Field Default Type Description Field Name Value EFBDATDBE EFB Data Double Bit Error. SWSticky When this bit is set, the corresponding error bit in the IERRORSTS0/1 register is masked from reporting an inter- nal error to the AER Capability Structure of the DMA func- tion.
Page 618 IDT DMA Function Registers Notes Field Default Type Description Field Name Value DIFBNPTLPTO DMA IFB Non-Posted TLP Time-Out. SWSticky When this bit is set, the corresponding error bit in the IERRORSTS0/1 register is masked from reporting an inter- nal error to the AER Capability Structure of the DMA func- tion.
Page 619 IDT DMA Function Registers Notes Field Default Type Description Field Name Value 30:29 Reserved This field is reserved but remains read-write in the hard- SWSticky ware. Modifying this field has no effect other than changing the value of the field. DE2EPE DMA End-to-End Data Path Parity Error.
Page 620 IDT DMA Function Registers Notes Field Default Type Description Field Name Value P9AER Port 9 AER Error. SWSticky When this bit is set, the corresponding error bit in the IERRORSTS0/1 register is masked from reporting an inter- nal error to the AER Capability Structure of the DMA func- tion.
Page 621 IDT DMA Function Registers DMA Multicast Control Notes MCRCVINT - Multicast Receive Interpretation (0x4FC) Field Default Type Description Field Name Value MCRCVINT Multicast Receive Interpretation. SWSticky This bit controls whether multicast TLPs emitted by the DMA (i.e., posted TLPs whose address falls within a multi- cast BAR aperture in the upstream port’s PCI-to-PCI bridge or NT functions) are transmitted on the upstream port’s link.
Page 622 IDT DMA Function Registers DMA Channel Registers Notes DMAC[1:0]CTL - DMA Channel Control (0x500/600) Field Default Type Description Field Name Value Run. Writing a one into this bit position initiates DMA descriptor processing if the DMA channel is idle and the E bit in the DMACxSTS register is cleared.
Page 623 IDT DMA Function Registers Notes Field Default Type Description Field Name Value DISDPTRH Disable DMACxDPTRH Descriptor Processing Initia- tion. When this bit is set, initiation of DMA descriptor processing as a side-effect writing to the DMACxDPTRH register is dis- abled. DISNDPTRL Disable DMACxNDPTRL Descriptor Processing Initia- tion.
Page 624 IDT DMA Function Registers Notes Field Default Type Description Field Name Value DRNS Descriptor Read No Snoop. This field specifies the state of the no snoop attribute in descriptor read operations. DWRO Descriptor Write Relaxed Ordering. This field specifies the state of the relaxed ordering attribute in descriptor write operations.
Page 625 IDT DMA Function Registers Notes Field Default Type Description Field Name Value RW1C Halt. This bit is set when the DMA channel halts descriptor pro- cessing. Once set, this bit is never cleared by hardware. RW1C Suspend. This bit is set when the DMA channel suspends descriptor processing.
Page 626 IDT DMA Function Registers Notes DMAC[1:0]ERRSTS - DMA Channel Error Status (0x510/610) Field Default Type Description Field Name Value DSCA RW1C Descriptor Alignment Error. De-featured. DSCP RW1C Descriptor Poisoned Error. This bit is set when a poisoned completion is received in response to a descriptor read request.
Page 627 IDT DMA Function Registers Notes Field Default Type Description Field Name Value DATCA RW1C Data Completer Abort Error. This bit is set when a completion with status CA is received in response to a data read request. Refer to section Completion with CA Status Received on page 15-34 for details.
Page 628 IDT DMA Function Registers Notes Field Default Type Description Field Name Value 15:10 Reserved Reserved field. DATP Data Poisoned Error. When this bit is set, the corresponding bit in the DMACx- ERRSTS register is masked from setting the Error (E) bit in the DMACxSTS register.
Page 629 IDT DMA Function Registers Notes DMAC[1:0]SSCTL - DMA Channel Source Stride Control (0x51C/61C) Field Default Type Description Field Name Value 15:0 SDIST Stride Distance. This field specifies the DMA channel stride distance in bytes. This value in this field is a signed number in two’s complement notation.
Page 630 IDT DMA Function Registers Notes Field Default Type Description Field Name Value 31:16 Reserved Reserved field. DMAC[1:0]DPTRL - DMA Channel Descriptor Pointer Low (0x528/628) Field Default Type Description Field Name Value 31:0 DPTRL Descriptor Pointer Low. This field is initialized with the lower 32-bits of the 64-bit address of the first DMA descriptor in a descriptor list.
Page 631: Global Address Space Access Registers
IDT DMA Function Registers Notes DMAC[1:0]NDPTRL - DMA Channel Next Descriptor Pointer Low (0x530/630) Field Default Type Description Field Name Value 31:0 NDPTRL Next Descriptor Pointer Low. This field is initialized with the lower 32-bits of the 64-bit address of the first DMA descriptor in the chaining descrip- tor list.
Page 632 IDT DMA Function Registers Notes Field Default Type Description Field Name Value 18:2 GADDR Global Address. This field selects the system address of the register to be accessed via the GASADATA register. The following restrictions apply regarding the programming of this register: 1) The value of this register must not be programmed to point to the address of the GASAADDR or GASADATA reg- ister in this or any other function.
Page 633: Switch Configuration And Status Registers
Chapter 24 Switch Configuration and Status Registers ® Switch Control and Status Registers Notes SWCTL - Switch Control (0x0000) Field Default Type Description Field Name Value Reserved Reserved field. RSTHALT HWINIT Reset Halt. SWSticky When this bit is set, all of the switch logic except the SMBus interface remains in a quasi-reset state.
Page 634 IDT Switch Configuration and Status Registers Notes BCVSTS - Boot Configuration Vector Status (0x0004) Field Default Type Description Field Name Value SWMODE HWINIT Switch Mode. Boot configuration vector value sampled during a switch fundamental reset. Reserved Reserved field. GCLKFSEL HWINIT Global Clock Frequency Select.
Page 635 IDT Switch Configuration and Status Registers Notes PCLKMODE - Port Clocking Mode (0x0008) Field Default Type Description Field Name Value Reserved Reserved field. P8CLKMODE Ports 8 to 11 Clocking Mode. SWSticky This field selects the port clocking mode used by the corre- sponding switch port(s).
Page 636: Internal Switch Timers
IDT Switch Configuration and Status Registers Notes STK3CFG - Stack Configuration (0x001C) Field Default Type Description Field Name Value STKCFG HWINIT Stack Configuration. SWSticky This field selects the configuration of the stack. The initial value of this field depends on the setting of the STK3CFG pins, as described in section Stack Configuration on page 3-5.
Page 637 IDT Switch Configuration and Status Registers Notes SEDELAY - Side Effect Delay (0x0088) Field Default Type Description Field Name Value 15:0 SEDELAY 0x03E8 Side Effect Delay SWSticky This field specifies the delay in microseconds from the gen- eration of a completion for a configuration request with an associated side-effect to the side effect action taking place.
Page 638 IDT Switch Configuration and Status Registers Switch Partition and Port Registers Notes SWPART[3:0]CTL - Switch Partition x Control Field Default Type Description Field Name Value STATE HWINIT Switch Partition State. SWSticky This field controls the state of the switch partition. 0x0 - (disable) Disabled 0x1 - (active) Active 0x2 - reserved...
Page 639 IDT Switch Configuration and Status Registers Notes SWPART[3:0]STS - Switch Partition x Status Field Default Type Description Field Name Value RW1C Switch Partition State Change Initiated. SWSticky This bit is set when a switch partition state change is initi- ated. RW1C Switch Partition State Change Completed.
Page 640 IDT Switch Configuration and Status Registers Notes SWPART[3:0]FCTL - Switch Partition x Failover Control Field Default Type Description Field Name Value PFSTATE Primary Failover Switch Partition State SWSticky This field specifies the primary failover state of the partition. 0x0 - (disable) Disabled 0x1 - (active) Active 0x2 - reserved 0x3 - (reset) Reset...
Page 641 IDT Switch Configuration and Status Registers Notes Field Default Type Description Field Name Value Reserved Reserved field. 17:16 Operating Mode Change Action. SWSticky This field specifies the action taken when a modification is made to the operating mode of a port. 0x0 - (noaction) No action - preserve state 0x1 - (reset) Port reset - behavior associated with funda- mental reset...
Page 642 IDT Switch Configuration and Status Registers Notes Field Default Type Description Field Name Value LINKMODE HWINIT Link Mode. This field indicates the operating mode of the lanes for the link associated with the port when the link is up. The value of this field is undefined when the link is down.
Page 643 IDT Switch Configuration and Status Registers Notes SWPORT[19:16,11:8,3:0]FCTL - Switch Port x Failover Control Field Default Type Description Field Name Value PFMODE Primary Failover Port Mode. SWSticky This field specifies the primary failover port mode. On a primary failover event, the value of this field is trans- ferred to the MODE field of the SWPORTxCTL register.
Page 644: Failover Capability Registers
IDT Switch Configuration and Status Registers Notes Field Default Type Description Field Name Value 25:23 Reserved Reserved field. 30:26 SFDEVNUM Secondary Failover Device Number. SWSticky This field specifies the secondary failover device number. On a secondary failover event, the value of this field is transferred to the DEVNUM field of the SWPORTxCTL reg- ister.
Page 645 IDT Switch Configuration and Status Registers Notes FCAP[3:0]STS - Failover Capability x Status Field Default Type Description Field Name Value FMODE Failover Mode. SWSticky This field indicates the current failover mode. When a failover mode change is in progress, this field returns the new mode.
Page 646: Protection
IDT Switch Configuration and Status Registers Protection Notes GASAPROT - Global Address Space Access Protection (0x0700) Field Default Type Description Field Name Value 23:0 PORT Port. SWSticky Each bit in this field corresponds to a switch port. When a bit in this field is set, access to global address space using a GASADDR and GASADATA register pair from the port is disabled and fields in both registers become read-only with a value of zero.
Page 647 IDT Switch Configuration and Status Registers Switch Event Registers Notes Refer to section Switch Events on page 16-1 for details on the operation of these registers. SESTS - Switch Event Status (0x0C00) Field Default Type Description Field Name Value LINKUP Link Up Status.
Page 648 IDT Switch Configuration and Status Registers Notes Field Default Type Description Field Name Value P8AER RW1C Port 8 AER Error SWSticky This bit is set at the time that port 8 detects an AER error in one of its functions (i.e., any bit is set in the corresponding internal, non-software visible PAERSTS register) and the error is not masked by the corresponding Port AER Mask (PAERMSK) register.
Page 649 IDT Switch Configuration and Status Registers Notes SEMSK - Switch Event Mask (0x0C04) Field Default Type Description Field Name Value LINKUP Link Up. SWSticky When this bit is set, the corresponding bit in the SESTS register is masked from generating a switch event. LINKDN Link Down.
Page 650 IDT Switch Configuration and Status Registers Notes Field Default Type Description Field Name Value P16AER Port 16 AER Error. SWSticky When this bit is set, the corresponding bit in the SESTS register is masked from generating a switch event. P17AER Port 17 AER Error SWSticky When this bit is set, the corresponding bit in the SESTS...
Page 651: Switch Event Registers
IDT Switch Configuration and Status Registers Notes SELINKUPMSK - Switch Event Link Up Mask (0x0C10) Field Default Type Description Field Name Value 23:0 LINKUP 0xFF_FFFF Link Up. SWSticky When a bit in this field is set, the corresponding bit in the SELINKUPSTS register is masked from generating a switch event.
Page 652 IDT Switch Configuration and Status Registers Notes SEFRSTMSK - Switch Event Fundamental Reset Mask (0x0C20) Field Default Type Description Field Name Value FRST 0xFF Partition Fundamental Reset. SWSticky When a bit in this field is set, the corresponding bit in the SEFRSTSTS register is masked from generating a switch event.
Page 653 IDT Switch Configuration and Status Registers Notes SEFOVRMSK - Switch Event Failover Mask (0x0C2C) Field Default Type Description Field Name Value FCAP0FNCI Failover Capability 0 Failover Mode Change Initiated SWSticky Mask. When this bit is set, the Failover Mode Change Initiated (FMCI) bit in the Failover Capability 0 Status (FCAP0STS) register is masked from generating a switch event.
Page 654: Global Doorbells And Message Registers
IDT Switch Configuration and Status Registers Notes SEGSIGSTS - Switch Event Global Signal Status (0x0C30) Field Default Type Description Field Name Value GSIGNAL RW1C Global Signal. SWSticky Each bit in this field corresponds to a switch partition. A bit in this field is set when a global signal is generated from the corresponding partition.
Page 655: Serdes Control And Status Registers
IDT Switch Configuration and Status Registers Notes GIDBELLMSK[31:0] - NT Global Inbound Doorbell Mask [31:0] Field Default Type Description Field Name Value GIDBELLMSK Global Inbound Doorbell Mask. SWSticky Each bit in this field corresponds to a partition. When a bit in this field is set, the global doorbell corre- sponding to this register is masked from affecting the state of the inbound doorbell in the partition associated with this bit.
Page 656 IDT Switch Configuration and Status Registers Notes S[7:0]CTL- SerDes x Control Field Default Type Description Field Name Value LANESEL 0x10 Lane Select. SWSticky This field selects the lane on which the SerDes lane control registers (S[x]TXLCTL0, S[x]TXLCTL1, S[x]RXLCTL, and S[x]RXEQLCTL) operate when written. 0x0 - Operate on lane 0 only 0x1 - Operate on lane 1 only 0x2 - Operate on lane 2 only...
Page 657 IDT Switch Configuration and Status Registers Notes S[7:0]TXLCTL0 - SerDes x Transmitter Lane Control 0 Field Default Type Description Field Name Value FDC_FS3DBG1 Transmit Driver Fine De-emphasis Control for Full SWSticky Swing Mode with -3.5dB in Gen 1. This field provides fine level control of the transmit driver de-emphasis level in full-swing mode and Gen 1 data rate (i.e., 2.5 GT/s).
Page 658 IDT Switch Configuration and Status Registers Notes Field Default Type Description Field Name Value 17:6 Reserved Reserved field. 20:18 TX_SLEW_G1 Transmit Driver Slew Adjustment in Gen 1. SWSticky This field controls the output driver’s slew rate at Gen 1 data-rate, for the lane(s) selected by the Lane Select (LANESEL[3:0]) field in the SerDes Control (S[x]CTL) register.
Page 659 IDT Switch Configuration and Status Registers Notes S[7:0]TXLCTL1 - SerDes x Transmitter Lane Control 1 Field Default Type Description Field Name Value TDVL_FS3DBG1 0x12 Transmit Driver Voltage Level for Full-Swing Mode SWSticky with -3.5dB De-emphasis in Gen 1. This field controls the SerDes transmit driver voltage level in full-swing mode and Gen 1 data rate (i.e., 2.5 GT/s).
Page 660 IDT Switch Configuration and Status Registers Notes Field Default Type Description Field Name Value 15:13 CDC_FS3DBG2 Transmit Driver Coarse De-Emphasis Control for SWSticky Full Swing mode with -3.5dB in Gen 2. This field provides coarse level control of the transmit driver de-emphasis level in Gen 2 mode, when the SDE field in the associated port’s PCIELCTL2 register is set to -3.5dB de-emphasis.
Page 661 IDT Switch Configuration and Status Registers Notes Field Default Type Description Field Name Value 27:24 TDVL_LSG1 Transmit Driver Voltage Level for Low-Swing Mode SWSticky in Gen 1. This field controls the SerDes transmit driver voltage level when the associated port operates in low-swing mode (i.e., the LSE bit in the port’s SERDESCFG reg- ister is set to 0x1) and Gen 1 data rate.
Page 662: General Purpose I/O Registers
IDT Switch Configuration and Status Registers Notes S[7:0]RXEQLCTL - SerDes x Receiver Equalization Lane Control Field Default Type Description Field Name Value RXEQZ Receiver Equalization Zero. SWSticky Amplifies the high-frequency gain of the equalizer. Setting both RXEQZ and RXEQB to zero results in turning off the receiver equalization completely.
Page 663 IDT Switch Configuration and Status Registers Notes GPIOAFSEL - General Purpose I/O Alternate Function Select (0x1170) Field Default Type Description Field Name Value AFSEL0 GPIO Pin 0 Alternate Function Select. SWSticky This field selects the alternate function associated with the corresponding GPIO pin when the GPIO pin is configured to operate as an alternate function.
Page 664: Hot-Plug And Smbus Interface Registers
IDT Switch Configuration and Status Registers Notes GPIOD - General Purpose I/O Data (0x1178) Field Default Type Description Field Name Value GPIOD HWINIT GPIO Data. SWSticky Each bit in this field controls the corresponding GPIO pin. Reading this field returns the current value of each GPIO pin regardless of GPIO pin mode (i.e., alternate function or GPIO pin).
Page 665 IDT Switch Configuration and Status Registers Notes Field Default Type Description Field Name Value 10:9 PDETECT Presence Detect Control. SWSticky This field controls the manner in which presence of an adapter in a slot is reported to the hot-plug controller asso- ciated with a downstream switch port.
Page 666 IDT Switch Configuration and Status Registers Notes Field Default Type Description Field Name Value 15:14 RSTMODE Reset Mode. SWSticky This field controls the manner in which port reset outputs are generated. 0x0 - (pec) Power enable controlled reset output 0x1 - (pgc) Power good controlled reset output 0x2 - Reserved 0x3 - Reserved 23:16...
Page 667 IDT Switch Configuration and Status Registers Notes Field Default Type Description Field Name Value RW1C Invalid Configuration Block. SWSticky This bit is set when the master SMBus interface detects an invalid configuration block during serial EEPROM initializa- tion. The valid configuration blocks are: - Single double-word initialization sequence - Sequential double-word initialization sequence - Jump block...
Page 668 IDT Switch Configuration and Status Registers Notes Field Default Type Description Field Name Value RW1C Unmapped Register Error. SWSticky This bit is set if an attempt is made to access via serial EEPROM a register that is not defined in the global address space.
Page 669 IDT Switch Configuration and Status Registers Notes Field Default Type Description Field Name Value 21:20 MSMBMODE Master SMBus Mode. SWSticky The master SMBus contains internal glitch counters on the MSMBCLK and MSMBDAT signals that wait approximately 1uS before sampling or driving these signals. This field allows the glitch counter time to be reduced or entirely removed.
Page 670 IDT Switch Configuration and Status Registers Notes SMBUSCBHL - SMBus Configuration Block Header Log (0x11E8) Field Default Type Description Field Name Value BYTE0 Configuration Block Byte 0. This field contains byte 0 of the last serial EEPROM config- uration block processed normally by the SMBus master interface.
Page 671 IDT Switch Configuration and Status Registers Notes EEPROMINTF - Serial EEPROM Interface (0x1190) Field Default Type Description Field Name Value 15:0 ADDR EEPROM Address. SWSticky This field contains the byte address in the Serial EEPROM to be read or written. 23:16 DATA EEPROM Data.
Page 672 IDT Switch Configuration and Status Registers Notes Field Default Type Description Field Name Value 23:17 IOE2ADDR I/O Expander 2 Address. SWSticky This field contains the SMBus address assigned to I/O expander 2 on the master SMBus interface. Reserved Reserved field. 31:25 IOE3ADDR I/O Expander 3 Address.
Page 673 IDT Switch Configuration and Status Registers Notes Field Default Type Description Field Name Value 23:17 IOE10ADDR I/O Expander 10 Address. SWSticky This field contains the SMBus address assigned to I/O expander 2 on the master SMBus interface. Reserved Reserved field. 31:25 IOE11ADDR I/O Expander 11 Address.
Page 674 IDT Switch Configuration and Status Registers Notes Field Default Type Description Field Name Value 23:17 IOE18ADDR I/O Expander 18 Address. SWSticky This field contains the SMBus address assigned to I/O expander 18 on the master SMBus interface. Reserved Reserved field. 31:25 IOE19ADDR I/O Expander 19 Address.
Page 675: Temperature Sensor Registers
IDT Switch Configuration and Status Registers Notes GPESTS - General Purpose Event Status (0x11B4) Field Default Type Description Field Name Value 23:0 GPES General Purpose Event Status. Each bit in this field corresponds to a port. When a bit is set, the corresponding port is signaling a general purpose event by asserting the GPEN signal.
Page 676 IDT Switch Configuration and Status Registers Notes Field Default Type Description Field Name Value AMTH Above Middle Temperature Threshold Interrupt Enable. SWSticky When this bit is set and the corresponding bit in the Tem- perature Sensor Alarm (TMPALARM) register is set, the TMPSENSOR bit is set in the P2PINTSTS and NTINTSTS registers of all upstream port PCI-to-PCI bridge and NT functions respectively.
Page 677 IDT Switch Configuration and Status Registers Notes Field Default Type Description Field Name Value BMTH Below Middle Temperature Threshold. This field contains the current value of the corresponding field in the Temperature Sensor Alarm (TMPALARM) regis- ter. AMTH Above Middle Temperature Threshold. This field contains the current value of the corresponding field in the Temperature Sensor Alarm (TMPALARM) regis- ter.
Page 678 IDT Switch Configuration and Status Registers Notes Field Default Type Description Field Name Value ALTH RW1C Above Low Temperature Threshold. SWSticky This bit is set when the current temperature is above the threshold set in the Low Temperature Threshold (LTH) field in the Temperature Sensor Control (TMPCTL) register.
Page 679 IDT Switch Configuration and Status Registers Notes TMPADJ - Temperature Sensor Adjustment (0x11E0) Field Default Type Description Field Name Value OFFSET 0xC4 Offset. SWSticky Absolute temperature offset in degrees C. This two’s complement value is added to the temperature value returned by the temperature sensor to produce the reported temperature.
Page 680 IDT Switch Configuration and Status Registers Notes Field Default Type Description Field Name Value 27:24 ADJ6 Slope Adjustment 6. SWSticky 120+ degree adjustment. 30:28 Reserved Reserved field. ADJDOWN Slope Adjustment Down. SWSticky If cleared, slope adjustment values in these register repre- sent positive adjustments.
Page 681: Jtag Boundary Scan
Chapter 25 JTAG Boundary Scan ® Introduction Notes The JTAG Boundary Scan interface provides a way to test the interconnections between integrated circuit pins after they have been assembled onto a circuit board. There are two pin types present in the switch: AC-coupled and DC-coupled (also called AC and DC pins).
Page 682: Table 25.1 Jtag Pin Descriptions
IDT JTAG Boundary Scan Notes Pin Name Type Description JTAG_TRST_N Input JTAG RESET (active low) Asynchronous reset for JTAG TAP controller (internal pull-up) JTAG_TCK Input JTAG Clock Test logic clock. JTAG_TMS and JTAG_TDI are sampled on the rising edge. JTAG_TDO is output on the falling edge. JTAG_TMS Input JTAG Mode Select.
Page 683: Table 25.2 Boundary Scan Chain
IDT JTAG Boundary Scan Boundary Scan Chain Notes Function Pin Name Type Boundary Cell PCI Express Interface PE00RN[0] PE00RP[0] PE00TN[0] PE00TP[0] PE01RN[0] PE01RP[0] PE01TN[0] PE01TP[0] PE02RN[0] PE02RP[0] PE02TN[0] PE02TP[0] PE03RN[0] PE03RP[0] PE03TN[0] PE03TP[0] Table 25.2 Boundary Scan Chain (Part 1 of 3) PES12NT12G2 User Manual 25 - 3 July 10, 2013...
Page 684 IDT JTAG Boundary Scan Notes Function Pin Name Type Boundary Cell PCI Express PE08RN[0] Interface (Cont.) PE08RP[0] PE08TN[0] PE08TP[0] PE09RN[0] PE09RP[0] PE09TN[0] PE09TP[0] PE10RN[0] PE10RP[0] PE10TN[0] PE10TP[0] PE11RN[0] PE11RP[0] PE11TN[0] PE11TP[0] PE16RN[0] PE16RP[0] PE16TN[0] PE16TP[0] PE17RN[0] PE17RP[0] PE17TN[0] PE17TP[0] PE18RN[0] PE18RP[0] PE18TN[0] PE18TP[0]...
Page 685: Test Data Register (Dr)
IDT JTAG Boundary Scan Notes Function Pin Name Type Boundary Cell System Pins CLKMODE[1:0] GCLKFSEL STK2CFG0 STK2CFG1 STK2CFG2 STK2CFG3 STK3CFG0 STK3CFG1 STK3CFG2 STK3CFG3 STK3CFG4 PERSTN RSTHALT SWMODE[3:0] — EJTAG / JTAG JTAG_TCK — JTAG_TDI — JTAG_TDO — JTAG_TMS — JTAG_TRST_N —...
Page 686: Figure 25.3 Diagram Of Observe-Only Input Cell
IDT JTAG Boundary Scan Notes Therefore, the SAMPLE/PRELOAD instruction must first be used to load suitable values into the boundary scan cells, so that inappropriate values are not driven out onto the system pins. All of the boundary scan cells feature a negative edge latch, which guarantees that clock skew cannot cause incor- rect data to be latched into a cell.
Page 687: Instruction Register (Ir)
IDT JTAG Boundary Scan Notes shift_dr EXTEST Output enable from core Data from previous cell OEN to pad clock_dr update_dr I/O pin shift_dr Data from core EXTEST To next cell Figure 25.5 Diagram of Bidirectional Cell The bidirectional cells are composed of only two boundary scan cells. They contain one output enable cell and one capture cell, which contains only one register.
Page 688: Extest
IDT JTAG Boundary Scan Notes Instruction Definition Opcode EXTEST Mandatory instruction allowing the testing of board level interconnec- 000000 tions. Data is typically loaded onto the latched parallel outputs of the boundary scan shift register using the SAMPLE/PRELOAD instruction prior to use of the EXTEST instruction. EXTEST will then hold these values on the outputs while being executed.
Page 689: Clamp
IDT JTAG Boundary Scan Notes Therefore, instead of having to shift many times to get a value through the device, the user only needs to shift one time to get the value from JTAG_TDI to JTAG_TDO. When the TAP controller passes through the CAPTURE-DR state, the value in the BYPASS register is updated to be 0.
Page 690: Extest_Pulse
IDT JTAG Boundary Scan Notes If the Run-Test/Idle state is not entered, the output of the AC pins is not distinguishable from the output of the DC EXTEST instruction. EXTEST_PULSE EXTEST_PULSE is an instruction listed in IEEE 1149.6 JTAG specification and is used to test AC pins during boundary scan by shifting data from TDI to TDO within the Shift-DR-TAP controller State.
Page 691: Usage Models
Chapter 26 Usage Models ® Introduction Notes This chapter describes possible configurations of the PES12NT12G2 switch and presents some impor- tant system usage models. The intent is to document important non-obvious device configuration proce- dures as well as usage models for the purpose of ensuring design correctness. For each configuration, a series of steps to configure the device is outlined without necessarily delving into a detailed description of each step.
Page 692: Port Clocking Configuration
IDT Usage Models Notes Stack 3 will operate with one x8 port. To achieve this configuration, the STK3CFG[4:0] pins of the device can be tied to the appropriate value (refer to Table 3.6) on the system board. Alternatively, regardless of the value of the STK3CFG[4:0] pins, the stack may be dynamically reconfigured via serial EEPROM as follows: 1.
Page 693: Boot-Time Switch Partitioning
IDT Usage Models Notes Root Complex Serial EEPROM CLKMODE[1:0] PES24NT6AG2 GCLK Figure 26.2 PES24NT6AG2 with Ports Operating in Different Clock Modes Description By default, all ports operate in global clocked mode. The CLKMODE[1:0] pins in the boot vector should be set to 0x1 to indicate that the upstream port of the switch operates in a common-clocked configuration with its link partner, while the downstream ports operate in a non-common clocked configuration with its link partner.
Page 694: Switch Partitioning Via Serial Eeprom
IDT Usage Models Switch Partitioning via serial EEPROM Notes Goal Configure switch partitions via the serial EEPROM (i.e., during switch fundamental reset). Assumptions – PES16NT8BG2 switch device. – Two partitions will be created: • Partition 0 has ports 0, 8, and 10. •...
Page 695: Switch Partitioning Via Pci Express Configuration Requests
IDT Usage Models Notes ing steps take place. 2. Ports 0, 8, and 10 are migrated to partition 0. Port 0 is configured as an upstream switch port in partition 0 by programming fields in the SWPORT0CTL register appropriately. Ports 8 and 10 are configured as downstream switch ports in partition 0 by programming fields in the SWPORT8CTL and SWPORT10CTL registers appropri- ately.
Page 696: Figure 26.4 Pes16Nt8Bg2 With Two Partitions Configured Via A Switch Manager Root Complex
IDT Usage Models Notes (Switch Manager) Switch Manager configures the Switch switch through the global address space registers (GASAADDR & GASADATA) in this P2P function (P2P) (P2P) Partition 0 Partition 1 (P2P) (P2P) (P2P) (P2P) Figure 26.4 PES16NT8BG2 with Two Partitions Configured via a Switch Manager Root Complex Description As dictated by the switch mode, all ports and partitions are initially in unattached mode (see section Unattached on page 5-8).
Page 697 IDT Usage Models Notes address space, and therefore configure switch partitions by accessing the switch partition con- trol (SWPARTxCTL) and switch port control (SWPORTxCTL) registers. Disables access by other ports to the GASAADDR and GASADATA registers by programming the GASAPROT register. This action ensures that no other agent connected to the switch via PCI Express is allowed to configure the switch.
Page 698: Dynamic Port And Partition Reconfiguration
IDT Usage Models Dynamic Port and Partition Reconfiguration Notes I/O Load Balancing: Downstream Port Migration Goal The purpose of this section is to: – Show the process of migrating a downstream port from one partition to another in an effort to perform I/O load balancing between two partitions.
Page 699 IDT Usage Models Notes When the switch manager device wishes to receive global signals from partitions 0 and 1, it configures the global signals mechanism as follows: – The SEGSIGMSK register is configured to unmask global signals from partitions 0 and 1. –...
Page 700 IDT Usage Models Notes The communication between the switch manager device and RC1 is done using the global signals mechanism as follows: – The switch manager writes to the NTSDATA register in port 16. The message is a system-specific message indicating that a root-complex should get ready to loose port 8 in the device. The encoding of such messages are outside the scope of this document.
Page 701: Non-Transparent Bridge (Ntb) Usage Models
IDT Usage Models Notes Switch Manager Switch (P2P) (P2P) ( NT) Partition 0 Partition 1 Partition 2 (P2P) (P2P) (P2P) (P2P) (P2P) (P2P) Figure 26.6 I/O Load Balancing Example: Switch Configuration after Port Migration Non-Transparent Bridge (NTB) Usage Models PES12NT12G2 as a Multiprocessor System Interconnect Goal Describe the process of interconnecting loosely-coupled multiprocessors using the switch’s non-trans- parent bridges.
Page 702: Figure 26.7 Multiprocessor System Interconnection Using The Pes12Nt12G2
IDT Usage Models Notes Switch Serial NT Interconnect EEPROM Partition 0 Partition 1 Partition 2 Partition 3 Figure 26.7 Multiprocessor System Interconnection Using the PES12NT12G2 Description The serial EEPROM preconfigures the switch partitions as shown in Figure 26.7. The serial EEPROM preconfigures the BARSETUP0 register in each NT function to map BARs 0/1 to the NT function’s config space.
Page 703 IDT Usage Models Notes The serial EEPROM preconfigures the NT messaging mechanism. In particular, it configures the manner in which messages issued by an NT function in a partition are transferred to NT functions in other partitions. During system operation, agents in each partition can communicate with each other using the switch’s NT messaging mechanism.
Page 704 IDT Usage Models Notes Each root-complex configures the NT lookup table in their corresponding NT function appropriately. For example, assume RC0 had received messages from RC1 indicating that it is allowed to transfer TLPs to a 256 KB window in RC1’s memory address range starting at address 0x4000_0000 (1 GB). Since BAR 2 is configured with a lookup table of 16 entries and a range of 1 MB, each table entry covers a range of 64 KB (see Table 14.2).
Page 705: Nt Crosslink & Nt Punch-Through
IDT Usage Models NT Crosslink & NT Punch-Through Notes Goal The purpose of this section is to: – Describe a system configuration with two switches, each connected to a root and two endpoints. The PES12NT12G2 switches are interconnected to each other via NT ports, forming a crosslink. –...
Page 706: Figure 26.9 System Configuration After Serial Eeprom Initialization
IDT Usage Models Notes Switch #1 Switch # 2 Port 0 Port 0 Serial NT Crosslink EEPROM ( NT) ( NT) Partition 0 Partition 0 Part 1 Part 1 (P2P) (P2P) (P2P) (P2P) Figure 26.9 System Configuration after Serial EEPROM Initialization Description The serial EEPROM configures switch #1 as shown in Figure 26.9.
Page 707: Dma Usage Models
IDT Usage Models Notes • BUS = 0x0, DEV = 0x0, FUNC = 0x0, {EREG, REG} = 0xFF8 – Write the following values to the PTCTL1 register in the NT function in port 8 of switch #1: • CFGTYPE = 0x0 (i.e., type 0 configuration access) •...
Page 708: Figure 26.10 System Configuration Immediately After Switch Fundamental Reset
IDT Usage Models Notes Switch Switch Switch ( UN) ( UN) ( UN) ( UN) ( UN) ( UN) Processor Processor Processor Node Node Node Figure 26.10 System Configuration Immediately after Switch Fundamental Reset The roots in the system start the PCI Express hierarchy discovery process. The root-complex connected to the transparent switch starts enumeration.
Page 709: Figure 26.11 Target System Configuration
IDT Usage Models Notes Switch Switch Switch ( NT) ( NT) ( NT) Port 0 Port 0 Port 0 Processor Processor Processor Node Node Node Figure 26.11 Target System Configuration The root-complex connected to the transparent switch completes enumeration. This root-complex views each processor node as an endpoint device with a single function (i.e., the NT function).
Page 710: Immediate Descriptor Usage
IDT Usage Models Immediate Descriptor Usage Notes Goal Describe the use of a DMA “immediate data transfer descriptor” in combination with NT doorbells as a mechanism to notify a target device of a completion of a DMA data transfer to the device (i.e., via interrupt generation).
Page 711: Figure 26.12 Active/Passive System Configuration Before Failover Event
IDT Usage Models Notes Description Fundamental reset is applied to the system. The switch boots in switch-mode “Multi-partition with Disabled ports and Serial EEPROM Initialization”. The serial EEPROM configures the switch as shown in Figure 26.12. – Port 0 is configured as an upstream switch port in partition 0. –...
Page 712 IDT Usage Models Notes • The FEN field in the SWPART4CTL and SWPORT6CTL registers is set to 0x1. – Ports 9 and 11 are configured to respond to primary and secondary failover events by program- ming fields in the SWPORT4FCTL and SWPORT6FCTL registers as follows: •...
Page 713: Active / Active Failover Configuration
IDT Usage Models Notes Primary Secondary Root Root (Passive) ( Active) Switch (P2P) Failover Signal Serial Partition 0 GPIO[4] Partition 1 EEPROM (Disabled) P 11 (P2P) (P2P) Figure 26.13 Active/Passive System Configuration after Failover Event The root complex connected to port 8 can now configure the PCI Express hierarchy. It is assumed that the root complex is aware that the failover operation has occurred, so that it may proceed to configure the PCI Express hierarchy associated with the switch’s port 8.
Page 714: Figure 26.14 Active/Active System Configuration Before Failover Event
IDT Usage Models Notes RC 0 Switch Serial Port 0 Port 8 EEPROM NT Interconnect PART0 PERSTN PART1 PERSTN Partition 0 Partition 1 (P2P) (P2P) (P2P) (P2P) EP11 EP16 EP18 Figure 26.14 Active/Active System Configuration Before Failover Event The serial EEPROM configures the GPIO pins 0 and 1 to operate in alternate function 0 mode. –...
Page 715 IDT Usage Models Notes • PFMODE = SFMODE = 0x5 (i.e., primary and secondary failover mode is set to unattached port) – Ports 16 and 18 are configured to respond to primary and secondary failover events by program- ming fields in the SWPORT12FCTL and SWPORT16FCTL registers as follows: •...
Page 716: Figure 26.15 Active/Active System Configuration Before Failover Event
IDT Usage Models Notes Switch Serial Port 8 EEPROM (UN) Partition 1 Partition 0 (Active) PART0 PERSTN PART1 PERSTN (P2P) (P2P) (P2P) (P2P) EP11 EP16 EP18 Figure 26.15 Active/Active System Configuration Before Failover Event If at a later timer the failed root is repaired or replaced, a partition fundamental reset in the partition connected to the failed root complex is expected.
Page 717: Failover With Two Crosslinked Pes12Nt12G2 Switches
IDT Usage Models Notes correct system operation, RC1 migrates the downstream ports 9 and 11 before modifying the operating mode of the upstream port 0. In this way, the root connected to the upstream port 0 will find a fully estab- lished partition during enumeration.
Page 718 IDT Usage Models Notes Description In each switch, the event signaling mechanism is configured to report link down events that occur on ports 0 and 8 to switch partitions 0 and 1. In switch #1, a link down event on port 0 is configured to be reported to partitions 0 and 1.
Page 719: Figure 26.17 System Configuration After Rc2 Modifies Port 8 In Switch #2
IDT Usage Models Notes At this point, port 8 is part of the PCI Express hierarchy in partition 0 of the #2 switch (i.e., a downstream switch port located in the virtual PCI bus of partition 0). Figure 26.17 shows the system configuration. RC2 can now send configuration request TLPs to the PCI-to-PCI bridge function in port 8 without having to access the switch’s global address space.
Page 720: Nt Multicasting
IDT Usage Models Notes • Given that the port operating mode action is set to ‘No Action’, the port operating mode change process does not affect the link between the two switches or the ability of RC2 to access the GASAADDR and GASADATA registers in function 0 of port 8 in switch #1.
Page 721: Figure 26.19 Pes12Nt12G2 With Port 0 Configured In Nt Function With Dma Mode And Ports 2, 8, And 16 In Nt Function Mode
IDT Usage Models Notes Assumptions The system is configured as shown in Figure 26.19. The data is to be NT multicasted from system memory in the root complex associated with switch partition 0 (i.e., RC0) to memory in the root complex associated with switch partitions 1 to 3.
Page 722: Figure 26.20 Pes12Nt12G2 With Port 0 Configured In Nt Function With Dma Mode And Ports 2, 8, And 16 In Nt Function Mode
IDT Usage Models Notes For example, RC2 uses NT multicast overlay register set 0, programs the overlay address to base 0x0510_0000, and programs the overlay requester ID to match that of the NT function in port 8. Also, RC3 uses NT multicast overlay register set 0, programs the overlay address to base 0x0820_0000, and programs the overlay requester ID to match that of the NT function in port 16.
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