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IDT Switch Partitions
Notes
PES48H12G2 User Manual
A partition with one upstream port and no downstream ports has the following behavior.
– All received requests, except configuration requests that target the upstream port, are treated as
unsupported requests.
– All received completions are treated as unsupported requests.
– The upstream port is allowed to enter and exit L0s and L1 ASPM state without regard to the ASPM
state of a downstream port (i.e., since there are no downstream ports, they play no role in deter-
mining when an upstream port enters or exists a low power ASPM state).
A partition with no upstream switch port and zero or more downstream ports operates in a manner
similar to that of a PCIe switch when the DLDHRST bit set in the SWPARTxCTL register and the data link
layer of the upstream port transitions to the DL_Down state (see section Partition Hot Reset on page 5-9 for
details).
– Peer-to-peer TLP transfers between downstream ports are allowed to progress.
– TLPs not destined to a downstream port are treated as unsupported requests.
– TLPs generated by the switch and that are normally routed to the root (e.g., INTx messages) are
silently discarded.
– Downstream ports are allowed to enter and exit L0s and L1 ASPM state without regard to the
ASPM state of the upstream port (i.e., since there is no upstream port, then upstream port plays
no role in determining when a downstream port enters or exists a low power ASPM state).
Partition State
A partition may be in one of three states: disabled, fundamental reset, and active. The state of a partition
is determined by the State (STATE) field in the Switch Partition Control (SWPARTxCTL) register. Valid state
transitions are shown in Figure 6.1. State transitions other than those shown in Figure 6.1 produce unde-
fined results.
Disabled
Any State
Figure 6.1 Allowable Partition State Transitions
Disabled
A partition in the disabled state represents unused and idle resources. Ports associated with a disabled
partition are in a disabled mode (see section Disabled on page 6-2) regardless of the value of the Mode
(MODE) field in the Switch Port Control (SWPORTxCTL) register.
Fundamental Reset
A partition in the fundamental reset state operates in the same manner as a traditional PCIe component
would when with the fundamental reset (PERSTN) signal asserted. This corresponds to a partition funda-
mental reset. See section Partition Fundamental Reset on page 5-8 for a details. The fundamental reset
state provides a software mechanism for resetting all logic and ports associated with a partition. Register
values are initialized on entry to the fundamental reset state. Following initialization, register values may be
modified by masters in other partitions or via an external SMBus master.
Fundamental
Reset
6 - 2
Active
April 5, 2013
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