Renesas mPD98410 Manuals

Manuals and User Guides for Renesas mPD98410. We have 1 Renesas mPD98410 manual available for free PDF download: User Manual

Renesas mPD98410 User Manual

Renesas mPD98410 User Manual (211 pages)

1.2G ATM SWITCH LSI

Brand: Renesas | Category: Switch | Size: 1 MB

Table of Contents

Table of Contents
9
Chapter 1 General

17
- Features
  17
- Ordering Information
  17
- Example of System Configuration (Application)
  18
- Block Diagram
  19
- Pin Configuration
  20
Chapter 2 Pin Functions

21
- Pin Configuration (Bottom View)
  21
- Pin Layout
  23
- Pin Functions
  29
- Power Supply
  29
- UTOPIA Interface
  30
- Memory Interface Signals
  34
- Microprocessor Interface Signals
  36
- Jtag
  38
- Others
  38
- Recommended Connections of Unused Pins
  39
- Pin Status at Reset
  40
Chapter 3 Functional Outline

41
- UTOPIA Interfaces
  41
- Input Port Interface
  42
- Output Port Interface
  43
- Polling
  44
- Outline of Polling
  44
- Polling During Cell Output
  46
- Polling During Cell Input
  52
- Header Translation
  58
- HTT (Header Translation Table) Memory Map
  58
- General
  59
- Format of HTT
  62
- Accessing HTT
  65
- Flow of Header Translation
  70
- Accessing HTT with RM Cell
  74
- Queue Control
  77
- Single Cast
  77
- Multi-Cast
  78
- Congestion Control
  79
- Cell Discard by Class
  83
- EPD (Early Packet Discard) Control
  84
- PPD (Partial Packet Discard) Control
  86
- Minimum Queue Length
  87
- ABR Congestion Control
  90
- EFCI (Explicit Forward Congestion Indicator)
  90
- RM Cell CI/NI Marking (Resource Management Cell CI/NI Congestion Indication Marking)
  90
- RM Cell Merge (Resource Management Cell Merge)
  91
- WFQ (Weighted Fairness Queue)
  92
- General
  92
- Counters and Flags Used
  92
- Peak Rate Shaping Function
  95
- General
  95
- Details
  97
- Successive Transmission
  101
- Interrupt Request
  105
- Parity Error
  105
- Input Port Overrun
  105
- Queue Pointer Error
  105
- Cast Count Error
  106
- Cell Buffer Memory Shortage
  106
- Control Memory Shortage
  106
- HEC/CRC Error
  106
- Header Translation Error
  107
- Exceeding Buffer Threshold Value
  107
- Count over Detection
  107
- Monitoring
  108
- Monitor Register
  108
- Cell Discard Count Due to Exceeded Threshold Value
  108
- Cell Discard Count Due to Header Translation Error
  108
- Cell Discard Count Due to HEC Error or CRC Error
  109
- Cell Discard Count Due to Control/Cell Buffer Memory Shortage
  109
- Counting Number of Received Cells
  110
- Microprocessor Interface
  111
- I/O Mapping and Memory Mapping
  112
- 32-Bit Multiplexed Synchronous Bus (HSEL = Low)
  115
- 16-Bit Separated Asynchronous Bus (HSEL = High)
  117
- External Memory Interface
  120
- HTT & Control Memory Interface
  120
- Cell Buffer Interface
  121
Chapter 4 Internal Registers

125
Chapter 5 Jtag Boundary Scan

175
- Features
  175
- Internal Configuration of Boundary Scan Circuit
  176
- Instruction Register
  176
- TAP (Test Access Port) Controller
  176
- Bypass Register
  176
- Boundary Scan Register
  176
- Pin Function
  177
- JCK (JTAG Clock) Pin
  177
- JMS (JTAG Mode Select) Pin
  177
- JDI (JTAG Data Input) Pin
  177
- JDO (JTAG Data Output) Pin
  177
- JRST_B (JTAG Reset) Pin
  177
- Operation Description
  178
- TAP Controller
  178
- TAP Controller State
  178
- TAP Controller Operation
  183
- Initializing TAP Controller
  186
- Instruction Register
  186
- BYPASS Instruction
  187
- EXTEST Instruction
  187
- Boundary Scan Data Bit Definition
  187
Chapter 6 Limitations

189
- Limitations
  189
- Description of Limitations
  190
CHAPTER 7 FAQ (Frequently Asked Questions)

197

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