Physical Layer Errors; Data Link Layer Errors; Table 9.7 Physical Layer Errors; Table 9.8 Data Link Layer Errors - Renesas IDT 89HPES48H12G2 User Manual

IDT Theory of Operation
Notes
PES48H12G2 User Manual
A PCI-to-PCI Bridge function claims a TLP in the following cases:
– Address Routed TLPs: If received on the primary side of the bridge, the TLPs address falls within
the address space range(s) programmed in the base/limit registers. If received on the secondary
side of the bridge, always.
– ID Routed TLPs: If received on the primary side of the bridge, the TLPs destination ID matches
the bus aperture range programmed in the primary/secondary/subordinate registers or matches
the bridge function's bus/device/function assignment. If received on the secondary side of the
bridge, always.
– Implicit Route TLPs: Always.

Physical Layer Errors

Table 9.7 lists error checks performed by the physical layer and the action taken when an error is
detected. Physical layer errors affect all functions of the port.
Error Condition
Link Errors (8b/10b, loss of symbol
lock, elastic buffer overflow/underflow,
lane-to-lane deskew)
Any TLP or DLLP framing rule violation.

Data Link Layer Errors

Table 9.8 lists error checks performed by the data link layer and action taken when an error is detected.
Data link layer errors affect all functions of the port. Per the PCI Express 2.0 specification, data link layer
errors are ignored in cases where the error is associated with a received packet for which the physical layer
reports an error. This prevents error pollution.
Error Condition
1
Bad TLP
2
Bad DLLP
Replay time-out
REPLAY NUM rollover
3
DL Protocol Error
Surprise link down (refer to section
Link Down on page 7-10).
1.
A Bad TLP is a TLP ending in EDB with LCRC that does not match inverted calculated LCRC, or a TLP with incorrect LCRC, or a
TLP received with sequence number not equal to NEXT_RCV_SEQ and this is not a duplicate TLP)
2.
A bad DLLP is a DLLP with a bad LCRC.
PCIe Base
Function-
2.0
Specific
Specificatio
n Section
4.2.4.6
4.2.2

Table 9.7 Physical Layer Errors

PCIe Base
Function-
2.0
Specific
Specificatio
Error
n Section
3.5.3.1
3.5.2.1
3.5.2.1
3.5.2.1
3.5.2.1
3.5.2.1 & 3.2.1

Table 9.8 Data Link Layer Errors

9 - 7
Action Taken
Error
No Correctable error
processing
No Correctable error
processing
Action Taken
No TLP discarded, Correctable error
processing
No DLLP discarded, Correctable
error processing
No Correctable error processing
No Correctable error processing
No DLLP discarded, Uncorrectable
error processing
No Uncorrectable error processing
April 5, 2013