Renesas IDT 89HPES48H12G2 Manuals

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Renesas IDT 89HPES48H12G2 User Manual (315 pages)

PCI Express Switch

Brand: Renesas | Category: Switch | Size: 4.26 MB

About this Manual
3
Content Summary
3
Signal Nomenclature
4
Numeric Representations
4
Data Units
4
Register Terminology
5
Use of Hypertext
7
Reference Documents
7
Table of Contents
11
PES48H12G2 Device Overview
25
Introduction
25
Features
25
Logic Diagram
29
System Identification
30
Vendor ID
30
Device ID
30
Revision ID
30
Jtag ID
30
Ssid/Ssvid
30
Device Serial Number Enhanced Capability
30
PES48H12G2 Device Ids
30
Table 1.3 PES48H12G2 Revision ID
30
Pin Description
31
Table 1.4 PCI Express Interface Pins
31
Table 1.5 Reference Clock Pins
32
Table 1.6 Smbus Interface Pins
32
Table 1.7 General Purpose I/O Pins
33
Table 1.8 System Pins
34
Table 1.9 Test Pins
35
Table 1.10 Power, Ground, and Serdes Resistor Pins
36
Pin Characteristics
37
Table 1.11 Pin Characteristics
37
Architectural Overview
41
Introduction
41
Switch Partitioning
42
Dynamic Reconfiguration
43
Switch Core
45
Introduction
45
Switch Core Architecture
45
Ingress Buffer
45
Table 3.1 IFB Buffer Sizes
45
Egress Buffer
46
Table 3.2 EFB Buffer Sizes
46
Crossbar Interconnect
47
Datapaths
47
Table 3.3 Replay Buffer Storage Limit
47
Packet Ordering
48
Arbitration
49
Table 3.4 Packet Ordering Rules in the PES48H12G2
49
Port Arbitration
50
Cut-Through Routing
50
Table 3.5 Conditions for Cut-Through Transfers
51
Request Metering
52
Operation
54
Table 1.1 Table
54
Table 3.6 Request Metering Decrement Value
55
Completion Size Estimation
56
Internal Errors
57
Switch Time-Outs
58
Memory SECDED ECC Protection
58
End-To-End Data Path Parity Protection
58
Clocking
61
Port Clocking Modes
62
Spread Spectrum Clocking (SSC) Support
62
Table 4.1 Initial Port Clocking Mode and Slot Clock Configuration State
62
Table 4.2 GCLK and Pxclk Frequencies When Pxclk Has SSC
63
Table 4.3 Port Clocking Mode Requirements
63
Table 4.4 Valid PES48H12G2 System Clocking Configurations
63
Global Clocked Mode
64
Local Port Clocked Mode
65
Modification of a Port's Clock Mode
66
Table 4.5 Clock Frequency Limitations When Modifying a Port's Clock Mode
66
Reset and Initialization
67
Introduction
67
Table 5.1 PES48H12G2 Reset Precedence
67
Boot Configuration Vector
68
Table 5.2 Boot Configuration Vector Signals
68
Switch Fundamental Reset
69
Switch Mode Dependent Initialization
72
Table 5.3 Switch Mode Dependent Register Initialization
72
Port Merging
73
Partition Resets
74
Partition Fundamental Reset
74
Partition Hot Reset
75
Partition Upstream Secondary Bus Reset
75
Partition Downstream Secondary Bus Reset
76
Port Mode Change Reset
76
Switch Partitions
77
Introduction
77
Partition Configuration
77
Partition State
78
Partition State Change
79
Switch Ports
80
Switch Port Mode
80
Port Operating Mode Change
83
Common Operating Mode Change Behavior
85
No Action Mode Change Behavior
90
Reset Mode Change Behavior
90
Hot Reset Mode Change Behavior
91
Partition and Port Configuration
91
Static Reconfiguration
91
Dynamic Reconfiguration
92
Link Operation
95
Introduction
95
Polarity Inversion
95
Lane Reversal
95
Link Width Negotiation
99
Link Width Negotiation in the Presence of Bad Lanes
100
Dynamic Link Width Reconfiguration
100
Link Speed Negotiation
100
Link Speed Negotiation in the PES48H12G2
101
Software Management of Link Speed
102
Link Retraining
103
Link down
104
Slot Power Limit Support
104
Upstream Port
104
Downstream Port
104
Link States
105
Active State Power Management
105
L0S ASPM
106
L1 Aspm
106
L1 ASPM Entry Rejection Timer
107
Link Status
108
De-Emphasis Negotiation
108
Crosslink
109
Table 7.1 Crosslink Port Groups
109
Hot Reset Operation on a Crosslink
110
Link Disable Operation on a Crosslink
110
Gen1 Compatibility Mode
110
Table 7.2 Gen1 Compatibility Mode: Bits Cleared in Training Sets
111
Serdes
113
Introduction
113
Serdes Numbering and Port Association
113
Serdes Transmitter Controls
113
Driver Voltage Level and Amplitude Boost
113
De-Emphasis
114
Slew Rate
114
PCI Express Low-Swing Mode
114
Receiver Equalization
115
Programming of Serdes Controls
115
Programmable Voltage Margining and De-Emphasis
115
Serdes Transmitter Control Registers
116
Table 8.1 Serdes Transmit Level Controls in the S[X]Txlctl0 and S[X]Txlctl1 Registers
117
Table 8.2 Serdes Transmit Driver Settings in Gen1 Mode
118
Table 8.3 Serdes Transmit Driver Settings in Gen2 Mode with -3.5Db De-Emphasis
119
Table 8.4 Serdes Transmit Driver Settings in Gen2 Mode with -6.0Db De-Emphasis
120
Table 8.5 Transmitter Slew Rate Settings
123
Transmit Margining Using the PCI Express Link Control 2 Register
124
Table 8.6 PCI Express Transmit Margining Levels Supported by the PES48H12G2
124
Low-Swing Transmitter Voltage Mode
125
Table 8.7 Serdes Transmit Drive Swing in Low Swing Mode at Gen1 Speed
125
Receiver Equalization Controls
126
Table 8.8 Serdes Transmit Drive Swing in Low Swing Mode at Gen2 Speed
126
Serdes Power Management
127
Theory of Operation
129
Introduction
129
Transaction Routing
129
Interrupts
129
Table 9.1 Switch Routing Methods
129
Downstream Port Interrupts
130
Legacy Interrupt Emulation
130
Table 9.2 Downstream Port Interrupts
130
Access Control Services
131
Table 9.3 Downstream to Upstream Port Interrupt Routing Based on Device Number
131
Table 9.4 Prioritization of ACS Checks for Request Tlps
133
Error Detection and Handling
134
Table 9.5 Prioritization of ACS Checks for Completion Tlps
134
Table 9.6 TLP Types Affected by ACS Checks
134
Physical Layer Errors
135
Data Link Layer Errors
135
Table 9.7 Physical Layer Errors
135
Table 9.8 Data Link Layer Errors
135
Transaction Layer Errors
136
Table 9.9 Transaction Layer Errors Associated with the PCI-To-PCI Bridge Function
137
Table 9.10 Conditions Handled as Unsupported Requests (UR) by the PCI-To-PCI Bridge Function
139
Table 9.11 Ingress TLP Formation Checks Associated with the PCI-To-PCI Bridge Function
139
Table 9.12 Egress Malformed TLP Error Checks
140
Table 9.13 ACS Violations for Ports Operating in Downstream Switch Port Mode
141
Table 9.14 Prioritization of Transaction Layer Errors
142
Table 10.1 Table
143
Routing Errors
144
Bus Locking
145
Hot-Plug and Hot-Swap
149
Introduction
149
Hot-Plug Signals
151
Port Reset Outputs
153
Power Enable Controlled Reset Output
153
Hot-Plug Events
154
Legacy System Hot-Plug Support
155
Hot-Swap
156
Power Management
157
Introduction
157
Table 11.1 PES48H12G2 Power Management State Transition Diagram
158
PME Messages
159
PCI Express Power Management Fence Protocol
159
Upstream Switch Port or Downstream Switch Port Mode
159
Power Budgeting Capability
160
General Purpose I/O
161
Introduction
161
GPIO Configuration
161
Configured as an Input
161
Configured as an Output
161
Configured as an Alternate Function
161
Table 12.1 GPIO Pin Configuration
161
Table 12.2 General Purpose I/O Pin Alternate Function
162
Table 12.3 GPIO Alternate Function Pins
162
Smbus Interfaces
163
Introduction
163
Master Smbus Interface
163
Initialization
163
Serial EEPROM
163
Figure 13.1 Split Smbus Interface Configuration
163
Initialization from Serial EEPROM
164
Table 13.1 PES48H12G2 Compatible Serial Eeproms
164
Figure 13.2 Single Double Word Initialization Sequence Format
165
Figure 13.3 Sequential Double Word Initialization Sequence Format
165
Figure 13.4 Configuration Done Sequence Format
166
Programming the Serial EEPROM
167
I/O Expanders
167
Table 13.2 Serial EEPROM Initialization Errors
167
Table 13.3 I/O Expander Function Allocation
168
Table 13.4 I/O Expander Default Output Signal Value
169
Table 13.7 Pin Mapping I/O Expander 9
172
Table 13.9 I/O Expander 11 - Partition Fundamental Reset Inputs
174
Table 13.10 I/O Expander 12 - Link up Status
174
Slave Smbus Interface
175
Table 13.11 I/O Expander 13 - Link Activity Status
175
Initialization
176
Smbus Transactions
176
Table 13.12 Slave Smbus Address
176
Figure 13.5 Slave Smbus Command Code Format
176
Table 13.13 Slave Smbus Command Code Fields
177
Table 13.14 CSR Register Read or Write Operation Byte Sequence
177
Table 13.15 CSR Register Read or Write CMD Field Description
178
Figure 13.6 CSR Register Read or Write CMD Field Format
178
Table 13.16 Serial EEPROM Read or Write Operation Byte Sequence
179
Table 13.17 Serial EEPROM Read or Write CMD Field Description
180
Figure 13.7 Serial EEPROM Read or Write CMD Field Format
180
Figure 13.8 CSR Register Read Using Smbus Block Write/Read Transactions with PEC Disabled
180
Figure 13.9 Serial EEPROM Read Using Smbus Block Write/Read Transactions with PEC
181
Figure 13.10 CSR Register Write Using Smbus Block Write Transactions with PEC Disabled
181
Figure 13.11 Serial EEPROM Write Using Smbus Block Write Transactions with PEC Disabled
181
Figure 13.12 Serial EEPROM Write Using Smbus Block Write Transactions with PEC Enabled
181
Figure 13.13 CSR Register Read Using Smbus Read and Write Transactions with PEC Disabled
182
Multicast
183
Introduction
183
Addressing and Routing
183
Multicast TLP Determination
183
Figure 14.1 Multicast Group Address Ranges
184
Figure 14.2 Multicast Group Address Region Determination
185
Multicast TLP Routing
186
Multicast Egress Processing
186
Register Organization
189
Introduction
189
Table 15.1 Global Address Space Organization
189
Partial-Byte Access to Word and Dword Registers
190
Register Side-Effects
190
Address Maps
190
PCI-To-PCI Bridge Registers
191
Capability Structures
191
Table 15.2 Default PCI Capability List Linkage
192
Table 15.3 Default PCI Express Capability List Linkage
192
Figure 15.1 PCI-To-PCI Bridge Configuration Space Organization
193
Table 15.4 PCI-To-PCI Bridge Configuration Space Registers
194
IDT Proprietary Port Specific Registers
198
Figure 15.2 Proprietary Port Specific Register Organization
198
Table 15.5 Proprietary Port Specific Registers
199
Switch Configuration and Status Registers
200
Figure 15.3 Switch Configuration and Status Space Organization
200
Table 15.6 Switch Configuration and Status
201
PCI to PCI Bridge and Proprietary Port Specific Registers
207
Type 1 Configuration Header Registers
207
PCI Express Capability Structure
217
Power Management Capability Structure
233
Message Signaled Interrupt Capability Structure
235
Subsystem ID and Subsystem Vendor ID
237
Extended Configuration Space Access Registers
237
Advanced Error Reporting (AER) Enhanced Capability
238
Device Serial Number Enhanced Capability
247
PCI Express Virtual Channel Capability
248
Power Budgeting Enhanced Capability
253
ACS Extended Capability
255
Multicast Extended Capability
258
Proprietary Port Specific Registers
263
Port Control and Status Registers
263
Internal Error Control and Status Registers
265
Physical Layer Control and Status Registers
273
Power Management Control and Status Registers
276
Request Metering
276
Global Address Space Access Registers
278
Switch Configuration and Status Registers
281
Switch Control and Status Registers
281
Internal Switch Timer
284
Switch Partition and Port Registers
284
Protection
287
Serdes Control and Status Registers
288
General Purpose I/O Registers
295
Hot-Plug and Smbus Interface Registers
297
JTAG Boundary Scan
305
Introduction
305
Test Access Point
305
Signal Definitions
305
Figure 18.1 Diagram of the JTAG Logic
305
Table 18.1 JTAG Pin Descriptions
306
Figure 18.2 State Diagram of the TAP Controller
306
Boundary Scan Chain
307
Table 18.2 Boundary Scan Chain
307
Test Data Register (DR)
309
Boundary Scan Registers
309
Figure 18.3 Diagram of Observe-Only Input Cell
309
Figure 18.4 Diagram of Output Cell
310
Figure 18.5 Diagram of Bidirectional Cell
310
Instruction Register (IR)
311
Extest
311
Table 18.3 Instructions Supported by the JTAG Boundary Scan
311
Sample/Preload
312
Bypass
312
Clamp
312
Idcode
312
Table 18.4 System Controller Device Identification Register
312
Figure 18.6 Device ID Register Format
312
Validate
313
Extest_Train
313
Extest_Pulse
313
Reserved
313
Usage Considerations
313

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Renesas IDT 89HPES48H12G2 User Manual (315 pages)

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