Low-Swing Transmitter Voltage Mode; Table 8.7 Serdes Transmit Drive Swing In Low Swing Mode At Gen1 Speed - Renesas IDT 89HPES48H12G2 User Manual

IDT SerDes
Notes
PES48H12G2 User Manual
Finally, when the TM field is modified, the newly selected value is not applied until the PHY LTSSM tran-
sitions through the states in which it is allowed to modify the transmit margin setting on the line (e.g.,
Recovery.RcvrLock). Therefore, after modifying this field, it is recommended that the link be retrained by
setting the LRET bit in the port's PCIELCTL register.

Low-Swing Transmitter Voltage Mode

The PES48H12G2 ports support the optional low-swing transmit voltage mode defined in the PCI
Express 2.0 specification. In this mode, the transmitter's voltage level is set to approximately half the value
of the full-swing (default) mode, which reduces power consumption in the SerDes. This mode is enabled by
setting the Low-Swing Enable (LSE) bit in the SerDes Configuration register.
– For a merged port, the LSE bit must be set in the SerDes Configuration register of both of the
SerDes associated with the port.
When Low-Swing mode is enabled, the transmitter drive level is reduced and de-emphasis is automati-
cally turned off. Therefore, the Selectable De-emphasis (SDE) and Compliance De-emphasis (CDE) fields
in the PCIELCTL2 register have no effect. Additionally, the Current De-emphasis (CDE) field in the
PCIELSTS2 register becomes invalid.
The low-swing mode transmitter voltage swing may be adjusted via the TDVL_LSG1 (when operating in
Gen1 mode) and TDVL_LSG2 (when operating in Gen2 mode) fields in the S[x]TXLCTL1 register. Table 8.7
shows the transmitter's drive swing for different values of TDVL_LSG1, when the port operates in low swing
1
mode at Gen1 speed . Table 8.8 shows the transmitter's drive swing for different values of TDVL_LSG2,
when the port operates in low swing mode at Gen2 speed. The default setting is highlighted.

Table 8.7 SerDes Transmit Drive Swing in Low Swing Mode at Gen1 Speed

1.
Table values are based on simulations using the Snowbush SerDes HSPICE model and device package s-
parameters. The simulation assumes typical conditions, with VddPEA = VddPETA = 1.0V, VddPEHA = 2.5V, and
TX_AMPBOOST = 0x2. Please refer to the device data sheet for post-silicon device characterization data.
Drive Level TDVL_LSG1
820 0x0F
785 0x0E
750 0x0D
714 0x0C
673 0x0B
632 0x0A
590 0x09
549 0x08
499 0x07
449 0x06
399 0x05
350 0x04
296 0x03
242 0x02
188 0x01
134 0x00
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