Clocking - Renesas IDT 89HPES48H12G2 User Manual

Notes
PES48H12G2 User Manual
®
Introduction
Figure 4.1 provides a logical representation of the PES48H12G2 clocking architecture. The
PES48H12G2 has a single differential global reference clock input (GCLK) as well as a differential refer-
ence clock input (P CLK) for ports 0 and 2. There are no ports 10 and 11 in the device.
[2,0]
Port 0
SerDes
Quad
Port 0
Stack
PLL
GCLK
Figure 4.1 Logical Representation of the PES48H12G2 Clocking Architecture
The differential global reference clock input (GCLK) is driven into the device on the GCLKP[1:0] and
GCLKN[1:0] pins.
– The nominal frequency of the global reference clock input may be selected by the Global Clock
Frequency Select (GCLKFSEL) pin to be either 100 MHz or 125 MHz.
• The GCLK supports SSC as described in section Spread Spectrum Clocking (SSC) Support on
page 4-2.
– Both global reference clock differential inputs should be driven with the same frequency. There
are no skew requirements between the GCLKP[0]/GCLKN[0] and GCLKP[1]/GCLKN[1] inputs.
Any constant phase difference is acceptable.
– The global reference clock input is provided to each SerDes quad and to an on-chip PLL.
• The on-chip PLL uses this clock to generate a 250 MHz core clock that is used by internal switch
logic (e.g., switch core, portion of a stack, etc.).
• The PLL within each SerDes quad generates a 5.0 GHz clock used by the SerDes analog
portion (PMA) and a 250 MHz clock used by the digital portion (PCS).
Associated with ports 0 and 2 are port reference clock inputs (PxCLK). Depending on the port clocking
mode (described below) a differential port reference clock input is driven into the device on the corre-
sponding PxCLKP and PxCLKN pins.
– The nominal frequency of the port's PxCLK is 100 Mhz, except in cases where the restrictions
outlined in section Modification of a Port's Clock Mode on page 4-6 apply. The PxCLK supports
SSC as described in section Spread Spectrum Clocking (SSC) Support on page 4-2.
...
Port 1 Port 2 Port 9
SerDes SerDes SerDes
Quad Quad Quad
Port 1 Port 2 Port 9
Stack Stack Stack
Switch Core
4 - 1
Chapter 4

Clocking

Port 12 Port 13
SerDes SerDes
Quad Quad
...
Port 12 Port 13
Stack Stack
April 5, 2013