Table of Contents
Advertisement
IDT Link Operation
Notes
PES48H12G2 User Manual
The actual link width is determined dynamically during link training. Ports limited to a maximum link
width of x8 are capable of negotiating to a x8, x4, x2, or x1 link width. The current negotiated width of a link
may be determined from the Negotiated Link Width (NLW) field in the corresponding port's PCI Express
Link Status (PCIELSTS) register.
To force a link width to a smaller width than the default value, the MAXLNKWDTH field could be config-
ured through Serial EEPROM initialization and full link retraining forced by setting the Full Link Retrain
(FLRET) bit in the port's PHYLSTATE0 register.
For details, refer to the description of the MAXLNKWDTH field in the PCIELCAP register in Chapter 16.
Link Width Negotiation in the Presence of Bad Lanes
In an effort to maximize the link width when one or more lanes of a multi-lane link are not functioning
correctly (i.e., reliable communication of training sets across the lane is not possible), PES48H12G2 down-
stream switch ports automatically attempt a lane reversed configuration when doing so has the potential to
enhance the achievable link width.
For example, if lane 1 of a x4 link is not operating correctly, the device's downstream switch port
attached to the link attempts a lane reversed configuration to form a x2 link using lanes 2 and 3 (Figure 7.4
(d)). If the link partner accepts the lane reversed configuration, the optimal x2 link will be formed using lanes
2 and 3. If the link partner does not accept the lane reversed configuration, but instead requests a lane
configuration supported by the PES48H12G2 (e.g., x1 link using lane 0), the device accepts the configura-
tion and forms the reduced width link. Otherwise, if the lane numbering agreement fails, the device auto-
matically re-trains the link from the Detect state. During this re-training, the PES48H12G2 port does not re-
attempt a lane reversed configuration, but rather tries to form the link without reversing the lanes. As a
result, a x1 link is formed using lane 0 (Figure 7.4 (e)).
Dynamic Link Width Reconfiguration
PES48H12G2 ports support dynamic link width upconfiguration and downconfiguration in response to
link partner requests. This capability is honored for regular links and crosslinks.
PES48H12G2 ports do not initiate autonomous link width upconfiguration and downconfiguration of
links, except for downconfiguration due to link reliability reasons (refer to Section Link Retraining on page 7-
9). Therefore, the Hardware Autonomous Width Disable (HAWD) bit in the port's PCIELCTL register has no
effect and is hardwired to 0x0. Additionally, the PES48H12G2 ports never set the 'Autonomous Change' bit
in the training sets exchanged with the link partner during link training.
A downstream port link partner may autonomously change link width. When this occurs, the
PES48H12G2 downstream port sets the Link Autonomous Bandwidth Status (LABWSTS) bit in the
PCIELSTS register.
Link Speed Negotiation
The PCI Express 2.0 specification introduces support for 5.0 GT/s data rates per lane (a.k.a., Gen2), in
addition to the 2.5 GT/s data rates (a.k.a, Gen1) mandated in previous versions of the specification. Per the
PCIe specification, all lanes of a link must operate at the same data rate. During full link training (i.e., from
the Detect state), links initially operate at 2.5 GT/s. Once the LTSSM on both components of the link reach
the L0 state and the data-link layer enters the DL_Active state, the link speed may be upgraded to 5.0 GT/s
if this capability is advertised by both components. The process of upgrading the link speed does not result
in a DL_Down state.
1.
Note that the 'Autonomous Change' bit is located in bit 6 of the fourth symbol in the training sets. This bit has
multiple meanings depending on the LTSSM state in which it is issued. PES48H12G2 never sets this bit in LTSSM
states in which this bit carries the 'autonomous change' meaning.
7 - 6
1
April 5, 2013
Advertisement
Table of Contents
