Table of Contents
Advertisement
IDT Clocking
There are no skew requirements between the global clock input and a port reference clock input or between any of the port reference clock inputs.
Port Clocking Modes
Port clocking refers to the clock that a port uses to receive and transmit serial data. The PES48H12G2 supports two port clocking modes. These
modes are described in section Global Clocked Mode on page 4-4 and section Local Port Clocked Mode on page 4-5. Ports are not required to all
operate in the same port clocking mode. A port may be independently configured to operate in any port clocking mode without regard to the mode of
any other port.
The port clocking mode used by a port is determined by the corresponding Port Clocking Mode (PxCLKMODE) field in the Port Clocking Mode
(PCLKMODE) register. The initial port clocking mode of a port is determined by the state of the CLKMODE[2:0] pins in the boot configuration vector as
shown in Table 4.1. This field also determines the initial value of the Slot Clock Configuration (SCLK) field in each port's PCI Express Link Status
(PCIELSTS) register. The SCLK field controls the advertisement of whether or not the port uses the same reference clock frequency as the link
partner.
CLKMODE[2:0]
Value in Boot
Configuration
Vector
0
1
2
3
4 - 7
Spread Spectrum Clocking (SSC) Support
The PES48H12G2 supports Spread Spectrum Clocking (SSC) for ports operating in the global clocked or local port clocked modes. The use of
SSC is optional. To use SSC, the following requirements apply.:
– If the GCLK has SSC, then all ports must operate in global clocked mode and be configured in a common clocked configuration with their
link partners.
– If the GCLK does not have SSC, then a port may be configured in global clocked mode or local port clocked mode.
– If a port is operating in local port clocked mode and the port's local clock (PxCLK) has SSC, the following must be met:
• The port must operate in a common-clocked configuration with its link partner.
• The global reference clock input (GCLK) must not use SSC.
• The GCLK's frequency must be equal to or faster than the PxCLK's frequency. This statement does not include the nominal +/-300 ppm
deviations on either of these clocks. For example, the GCLK's frequency may be 100 Mhz - 300ppm while the PxCLK's frequency is 100
Mhz + 300ppm. In addition, frequency increases, if any, introduced by the SSC component
the GCLK frequency. Table 4.2 shows some allowed GCLK and PxCLK combinations.
1.
Per the PCI Express Base Specification 2.0, the SSC component modulates the reference clock's frequency in the range +0/-5000 ppm.
PES48H12G2 User Manual
Port 0
Port 0
Clocking
Support Local
SCLK
Mode
Global Clocked
0
Global Clocked
1
Global Clocked
0
Global Clocked
1
Table 4.1 Initial Port Clocking Mode and Slot Clock Configuration State
Ports Other
Than 0 That
Port
SCLK
Port
Clocking
Global Clocked
0
Global Clocked
0
Global Clocked
1
Global Clocked
1
Reserved
4 - 2
Ports Other
Than 0 That Do
Port
Not Support
SCLK
Local Port
Clocking
Global Clocked
0
Global Clocked
0
Global Clocked
1
Global Clocked
1
1
on PxCLK must be correspondingly added to
April 5, 2013
Advertisement
Table of Contents
