Table of Contents
Advertisement
IDT Link Operation
Notes
PES48H12G2 User Manual
A component advertises its supported speeds via the Data Rate Identifier bits in the TS1 and TS2
training sets transmitted to its link partner during link training. The PCIe spec permits a component to
change its supported speeds dynamically. It is allowed for a component to advertise supported link speeds
without necessarily changing the link speed, via the Recovery LTSSM state.
A component determines the supported speeds of its link partner by examining the Data Rate Identifier
bits in the TS1/TS2 training sets received during link training, specifically in the Configuration.Complete and
Recovery.RcvrCfg states. The last advertisement received overrides any previously recorded value.
Either link component may request a link speed change due to software requests or link reliability
reasons (i.e., speed downgrade). Downstream components are further permitted to request link speed
changes due to autonomous hardware initiated mechanisms. A component must only initiate a link speed
change when it knows that its link partner supports the target speed via prior exchange of Training Sets.
Gen2 support is optional while Gen1 support is mandatory.
If neither component in the link advertises support for Gen2, then the link remains operating in Gen1
speed. If one component has advertised support for Gen1 and Gen2, and the other has advertised support
for Gen1 only, then the link will remain operating in Gen1 speed until the lesser speed component decides
to:
– Advertise support for Gen2 via the Recovery state without modifying the link speed. The link
remains operating at Gen1 speed.
– Transition the link speed to Gen2 via the Recovery.Speed state. The link will operate at Gen2
speed. In this case, the advertisement of Gen2 speed by both components is done implicitly in the
Recovery substates entered while modifying the link speed.
It is the responsibility of the upstream component of the link (i.e., switch downstream ports) to keep the
link at the target link speed or at the highest common speed supported by both components of the link,
whichever is lower. In addition, the upstream component must initiate a link speed upgrade if it has
recorded support for the higher speed by its link partner and software sets the Link Retrain bit in the
PCIELCTL register with a target link speed which is not equal to the current link speed. The upstream
component (i.e., switch downstream port) is capable of notifying software of link speed changes via the Link
Bandwidth Notification mechanism described in the PCI Express 2.0 specification.
Link Speed Negotiation in the PES48H12G2
PES48H12G2 ports support data rates of 5.0 GT/s and 2.5 GT/s. The highest data rate of each link is
determined dynamically, and depends on the following factors:
– Maximum link data rate supported by both components of the link
– The Target Link Speed set via the Link Control 2 Register (PCIELCTL2)
– The reliability of the link at 5.0 GT/s
By default, the Target Link Speed (TLS) of each port is set to 5.0 GT/s. Therefore, the PES48H12G2
ports advertise support for 2.5 GT/s and 5.0 GT/s during the link training process via training-sets.
– During normal operation, the TLS field should not be modified in an upstream port.
After a fundamental reset, each port link trains to the L0 state at 2.5 GT/s (Gen1). Once the data-link
layer reaches the DL_Active state, if the Target Link Speed indicates 5.0 GT/s (default value), the switch's
downstream ports automatically initiate link speed upgrade to 5.0 GT/s (Gen2) using the link speed change
mechanism described in PCI Express 2.0 specification. Upstream ports do not automatically initiate link
speed upgrade to Gen2.
– The Initial Link Speed Change Control (ILSCC) bit in a port's PHYLCFG0 register controls whether
the port automatically initiates a speed upgrade to Gen2. If the ILSCC bit is set, the port does not
automatically initiate a speed change to Gen2. Software may modify this bit to change the default
behavior.
– The Link Bandwidth Management Status (LBWSTS) bit in the PCIELSTS register of downstream
ports is not set since the initial link speed upgrade is not caused by a software directed link retrain
or due to link reliability issues.
7 - 7
April 5, 2013
Advertisement
Table of Contents
