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IDT Link Operation
Notes
PES48H12G2 User Manual
Link Down
When an upstream port's link goes down, it triggers a hot reset in the partition associated with the port,
as described in section Partition Hot Reset on page 5-9. In addition:
– All TLPs queued in the port's ingress frame buffer (IFB) are silently discarded.
– All TLPs queued in the port's replay buffer (EFB) are silently discarded.
When a downstream port's link goes down (i.e., the data-link layer transitions to the DL_Down state), the
following occurs:
– All TLPs queued in the port's ingress frame buffer (IFB) are silently discarded.
– All TLPs queued in the port's replay buffer (EFB) are silently discarded.
– Request TLPs received by other ports and destined to the logical bus number associated with the
link that is down are treated as Unsupported Requests (UR).
– All other TLPs received by the other ports and destined to the logical bus number associated with
the link that is down are silently discarded.
– The port handles all TLPs that target the port's function(s) normally.
• It is possible to perform configuration read and write operations to the logical function(s) asso-
ciated with that port.
When a link comes up, flow control credits for the configured size of the port's IFB queues are adver-
tised. A link down condition on a downstream port's link may cause the Surprise Down Error Status
(SDOENERR) bit to be set in the port's AER Uncorrectable Error Status (AERUES) register. The conditions
under which surprise down is reported are described in Section 3.2.1 of the PCI Express 2.0 Specification.
In addition to the exception conditions listed in Section 3.2.1of the PCI Express 2.0 specification, the
SDOENERR bit in a port's AERUES register is not set in the following cases:
– The partition associated with the port is placed in Disabled mode (section Partition State on page
6-2).
– The port is placed in Disabled mode (section Switch Port Mode on page 6-4).
– The port's link is fully retrained (i.e., PHY transitions to the Detect state) as a result of a port oper-
ating mode change action (section Port Operating Mode Change on page 6-7).
– The port's link is fully retrained via the FLRET bit in the PHYLSTATE0 register.
– The port's clocking mode is modified (section Port Clocking Modes on page 4-2).
Slot Power Limit Support
The Set_Slot_Power_Limit message is used to convey a slot power limit value from a downstream
switch port or root port to the upstream port of a connected device or switch.
Upstream Port
When a Set_Slot_Power_Limit message is received by an upstream port, then the fields in the message
are written to the PCI Express Device Capabilities (PCIEDCAP) register of that port.
– Byte 0 bits 7:0 of the message payload are written to the Captured Slot Power Limit Scale
(CSPLS) field.
– Byte 1 bits 1:0 of the message payload are written to the Captured Slot Power Limit Value
(CSPLV) field.
Downstream Port
A Set_Slot_Power_Limit message is sent by downstream switch ports when either of the following
events occur.
– A configuration write is performed to the corresponding PCIESCAP register when the link associ-
ated with the downstream port is up.
– A link associated with the downstream port transitions from a non-operational state to an opera-
tional (i.e., data-link layer up) state.
7 - 10
April 5, 2013
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