Pci To Pci Bridge And Proprietary Port Specific Registers; Type 1 Configuration Header Registers - Renesas IDT 89HPES48H12G2 User Manual

Type 1 Configuration Header Registers

VID - Vendor Identification Register (0x000)
Bit Field
Field Name
15:0
DID - Device Identification Register (0x002)
Bit Field
Field Name
15:0
PCICMD - PCI Command Register (0x004)
Bit Field
Field Name
0
1
2
3
4
PES48H12G2 User Manual
PCI to PCI Bridge and Proprie-
tary Port Specific Registers
®
Default
Type
Value
VID RO 0x111D
Default
Type
Value
DID RO -
Default
Type
Value
IOAE RW 0x0
MAE RW 0x0
BME RW 0x0
SSE RO 0x0
MWI RO 0x0
Description
Vendor Identification. This field contains the 16-bit vendor ID
value assigned to IDT.
Description
Device Identification. This field contains the 16-bit device ID
assigned by IDT to this bridge.
Description
I/O Access Enable. When this bit is cleared, the bridge does not
respond to I/O accesses from the primary bus specified by
IOBASE and IOLIMIT.
0x0 - (disable) Disable I/O space.
0x1 - (enable) Enable I/O space.
Memory Access Enable. When this bit is cleared, the bridge does
not respond to memory and prefetchable memory space access
from the primary bus specified by MBASE, MLIMIT, PMBASE and
PMLIMIT.
0x0 - (disable) Disable memory space.
0x1 - (enable) Enable memory space.
Bus Master Enable. When this bit is cleared, the bridge does not
issue requests (e.g., memory, I/O and MSIs since they are in-band
writes) on behalf of subordinate devices and handles these as
Unsupported Requests (UR). Additionally, the bridge handles non-
posted transactions in the upstream direction with a Unsupported
Request (UR) completion. This bit does not affect completions in
either direction or the forwarding of non memory or I/O requests.
0x0 - (disable) Disable request forwarding.
0x1 - (enable) Enable request forwarding.
Special Cycle Enable. Not applicable.
Memory Write Invalidate. Not applicable.
16 - 1
Chapter 16
April 5, 2013