Internal Switch Timer; Switch Partition And Port Registers - Renesas IDT 89HPES48H12G2 User Manual

IDT Switch Configuration and Status Registers

Internal Switch Timer

USSBRDELAY - Upstream Secondary Bus Reset Delay (0x008C)
Bit
Field Name
15:0
31:16 Reserved

Switch Partition and Port Registers

SWPART[13:12, 9:0]CTL - Switch Partition x Control
Bit
Field Name
1:0
2 DLDHRST
18:3 Reserved
19 Reserved
21:20 Reserved
31:22 Reserved
PES48H12G2 User Manual
Field Default
Type
Value
USSBR RW 0x0
SWSticky
RO 0x0
Field Default
Type
Value
STATE RW HWINIT
SWSticky
RW 0x0
SWSticky
RO 0x0
RW HWINIT
SWSticky
RW HWINIT
SWSticky
RO 0x0
Description
Side Effect Delay.This field specifies the delay in microseconds
from when a configuration request that initiates a secondary bus
reset is processed to the start of the secondary bus reset action.
The default value corresponds to no delay.
Decreasing this delay is discouraged, except for the cases explic-
itly listed in this specification.
Reserved field.
Description
Switch Partition State. This field controls the state of the switch
partition.
0x0 - (disable) Disabled
0x1 - (active) Active
0x2 - Reserved
0x3 - (reset) Reset
The initial value of this field depends on the Switch Mode selected
via the boot configuration vector. Refer to section Switch Mode
Dependent Initialization on page 5-6.
Disable Link Down Hot Reset. When this bit is set, hot resets due
to the data link layer of the upstream port transitioning to the
DL_Down state are disabled.
As a result, the DL_Down condition on the upstream port does not
cause a hot reset on the upstream port (i.e., the port's configuring
space is not affected) and the hot reset is not propagated to the
downstream ports in the partition.
Note that the upstream port's data-link and physical layers are not
affected by this bit.
Reserved field.
This field is unused in the switch and serves as a place holder for
the future.
This field is unused in the switch and serves as a place holder for
the future.
Reserved field.
17 - 4 April 5, 2013