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IDT SerDes
Notes
PES48H12G2 User Manual
tion, signal de-emphasis is turned off. Low-swing mode is a per-link feature, meaning that all lanes of the
port operate low-swing simultaneously. Refer to section Low-Swing Transmitter Voltage Mode on page 8-13
for details on enabling low-swing mode on a port.
Receiver Equalization
In addition to the transmitter controls described above, the PES48H12G2 SerDes also contains a
receiver equalizer to compensate for effects of channel loss on received signal (i.e., high-speed signal
degradation due to the combined effects of board traces, vias, connectors, and cables in the physical link).
In general, the channel has low-pass filter characteristics, which results in the degradation of high speed
signals. Receiver equalization may be used to compensate for the lossy attenuation effects of the channel
on high-speed signals.
Receiver equalization can be controlled on a per-lane basis. Each SerDes lane contains a receiver
equalization circuit. This circuit is a multi-stage programmable amplifier, where each stage is a peaking
equalizer with a different center frequency and programmable gain. Varying amounts of gain may be
applied depending on the overall frequency response of the channel loss.
For details on programming the receiver equalizer, refer to section Receiver Equalization Controls on
page 8-14. The PES48H12G2 places no restrictions on the time at which the equalizer settings may be
modified (e.g., the settings can be modified during normal operation of the link or while the link is being
tested).
Programming of SerDes Controls
The SerDes controls described above may be programmed by accessing IDT proprietary registers
within the PES48H12G2 switch. The registers may be programmed via any of the mechanisms allowed by
the PES48H12G2 (i.e., via PCI Express configuration accesses from a root, via EEPROM loading at boot-
time, or via the PES48H12G2's SMBus slave interface).
The following sections describe in detail the control registers associated with the SerDes and the
manner in which the SerDes controls are programmed.
Programmable Voltage Margining and De-Emphasis
The PES48H12G2 contains SerDes transmitter voltage controls on a per-port, per-SerDes, and per-lane
basis. There are two mechanisms to control the SerDes transmitter voltage level:
– Via the Transmit Margin (TM) field of the associated port's Link Control 2 Register (PCIELCTL2).
– Via the SerDes transmitter control registers
• Each SerDes quad has independent transmitter control registers
• The SerDes Lane Transmitter Control Registers (S[x]TXLCTL0 and S[x]TXLCTL1) provide
transmit driver controls per-lane.
• S[0]TXLCTL0 and S[0]TXLCTL1 are associated with SerDes 0, S[1]TXLCTL0 and
S[1]TXLCTL1 are associated with SerDes 1, and so on.
The selection of which of the two mechanism controls the SerDes transmit voltage is based on the
setting of the TM field in the associated port's PCIELCTL2 register. The port associated with a SerDes quad
is subject to the rules in section SerDes Numbering and Port Association on page 8-1.
1.
The S[x]TXLCTL0 and S[x]TXLCTL1 registers are used in conjunction with the SerDes Control (S[x]CTL)
register in order to apply the settings to a particular lane or all lanes of the SerDes. Please refer to the description
of the S[x]CTL register for further details.
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April 5, 2013
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