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IDT Link Operation
Notes
PES48H12G2 User Manual
During normal operation (i.e, not polling.compliance), de-emphasis selection is done during the
Recovery state. The downstream component of the link (i.e., switch upstream port or endpoint) advertises
its desired de-emphasis by transmission of training sets. The upstream component of the link (i.e., switch
downstream port or root-complex port) notes its link partner desired de-emphasis, and makes a decision
about the de-emphasis to be used in the link.
The PES48H12G2's upstream port physical layer advertises its desired de-emphasis based on the
setting of the port's SDE field in the PCIELCTL2 register. The upstream port always accepts the link-part-
ners decision on the de-emphasis to be used in the link. The PES48H12G2's downstream ports ignore the
link partner's desired de-emphasis, and always choose the de-emphasis setting in the SDE field of the
port's PCIELCTL2 register.
Crosslink
The PES48H12G2 ports support the optional crosslink capability specified in the PCI Express Base
Specification 2.0. Per this specification, a crosslink is established between two downstream ports or two
upstream ports. The PES48H12G2 ports are capable of establishing crosslink with any link partner,
including another PES48H12G2 port.
When crosslink is formed between two ports, the physical layer of one of the ports operates as an
upstream component (e.g., downstream lanes) while the physical layer of the other port operates as a
downstream component (e.g., upstream lanes). The determination of which of the two ports that form the
crosslink operates with upstream or downstream lanes depends on the link training process as specified in
the PCI Express Base Specification.
The Link Mode (LINKMODE) field in the SWPORTxSTS register associated with the PES48H12G2 port
indicates the current link mode (i.e., upstream or downstream lanes) of the port's physical layer. When two
PES48H12G2 ports are crosslinked to each other, it is recommended that the crosslink connection be done
among ports in different port groups, as shown in Table 7.1. In order for ports in the same port group (e.g.,
port 0 and port 4, port 3 and port 7, etc.) to form a crosslink, software must set the SEED field in the cross-
linked port's Phy PRBS Seed (PHYPRBS) register to different values.
Group 0
Note that when a PES48H12G2 upstream port is crosslinked to a link-partner's upstream port, neither
port may automatically initiate a link speed change to Gen 2, thereby resulting in a Gen 1 link. It is possible
to overcome this by setting the ILSCC bit in the PES48H12G2 upstream port's PHYLCFG0 register. By
setting this bit, the PES48H12G2 upstream port will initiate the link transition to Gen 2 speed.
Crosslink is enabled by default. Crosslink may be disabled by setting the Crosslink Disable (CLINKDIS)
bit in the port's Phy Link Configuration 0 (PHYLCFG0) register.
Port Groups
Group 1
Group 2
0
1
2
4
5
6
8
9
10
12
13
14
Table 7.1 Crosslink Port Groups
7 - 15
Group 3
3
7
11
15
April 5, 2013
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