Table 13.16 Serial Eeprom Read Or Write Operation Byte Sequence - Renesas IDT 89HPES48H12G2 User Manual

IDT SMBus Interfaces
Notes
PES48H12G2 User Manual
Bit
Name Type
Field
5 0
1
6 RERR Read-Only
and Clear
1
7 WERR Read-Only
and Clear
Table 13.15 CSR Register Read or Write CMD Field Description (Part 2 of 2)
1.
The RERR and WERR bits are driven by the switch as status bits that indicate whether or not the switch's SMBus slave in-
terface accepted the register read/write command (the switch accepts the access if it has the correct byte sequence). When a
byte sequence refers to a register offset that is not listed or is regarded as a reserve register, the RERR and WERR bits will be
set after a read or write operation is performed.
Serial EEPROM Read or Write Operation
Table 13.16 indicates the sequence of data as it is presented on the slave SMBus following the byte
address of the Slave SMBus interface.
Byte Field
Position Name
0 CCODE
1 BYTCNT
2 CMD
3 EEADDR
4 ADDRL
5 ADDRU
6 DATA

Table 13.16 Serial EEPROM Read or Write Operation Byte Sequence

The format of the CMD field is shown in Figure 13.7 and described in Table 13.17.
0 Reserved. Must be zero
Read Error. This bit is set if the last CSR read SMBus transaction
was not claimed by the device. Success indicates that the transaction
was claimed, not necessarily that the operation completed without
error.
Write Error. This bit is set if the last CSR write SMBus transaction
was not claimed by the device. Success indicates that the transaction
was claimed, not necessarily that the operation completed without
error.
Command Code. Slave Command Code field described in Table
13.13.
Byte Count. The byte count field is only transmitted for block type
SMBus transactions. SMBus word and byte accesses to not contain
this field. The byte count field indicates the number of bytes following
the byte count field when performing a write or setting up for a read.
The byte count field is also used when returning data to indicate the
number of following bytes (including status).
Command. This field contains information related to the serial
EEPROM transaction
Serial EEPROM Address. This field specifies the address of the
Serial EEPROM on the Master SMBus when the USA bit is set in the
CMD field. Bit zero must be zero and thus the 7-bit address must be
left justified.
Address Low. Lower 8-bits of the Serial EEPROM byte to access.
Address Upper. Upper 8-bits of the Serial EEPROM byte to access.
Data. Serial EEPROM value read or to be written.
13 - 17
Description
Description
April 5, 2013