Programming The Serial Eeprom; I/O Expanders; Table 13.2 Serial Eeprom Initialization Errors - Renesas IDT 89HPES48H12G2 User Manual

Pci express switch

Table of Contents

IDT SMBus Interfaces

Notes

PES48H12G2 User Manual

Error

Configuration Done Sequence checksum mis-

match with that computed

Invalid configuration block type

(only invalid type is 0x2)

An unexpected NACK is observed during a

master SMBus transaction

A misplaced START or STOP condition is

detected by the master SMBus interface

Serial EEPROM address rollover error

detected

Blank serial EEPROM detected

Programming the Serial EEPROM

The serial EEPROM may be programmed prior to board assembly or in-system via the slave SMBus

interface or a PCIe root. Programming the serial EEPROM via the slave SMBus is described in section

Serial EEPROM Read or Write Operation on page 13-17. A PCIe root may read and write the serial

EEPROM by performing configuration read and write transactions to the Serial EEPROM Interface

(EEPROMINTF) register.

To read a byte from the serial EEPROM, the root should configure the Address (ADDR) field in the

EEPROMINTF register with the byte address of the serial EEPROM location to be read and the Operation

(OP) field to "read." The Busy (BUSY) bit should then be checked. If the EEPROM is not busy, then the read

operation may be initiated by performing a write to the Data (DATA) field. When the serial EEPROM read

operation completes, the Done (DONE) bit in the EEPROMINTF register is set and the busy bit is cleared.

When this occurs, the DATA field contains the byte data of the value read from the serial EEPROM.

To write a byte to the serial EEPROM, the root should configure the ADDR field with the byte address of

the serial EEPROM location to be written and set the OP field to "write." If the serial EEPROM is not busy

(i.e., the BUSY bit is cleared), then the write operation may be initiated by writing the value to be written to

the DATA field. When the write operation completes, the DONE bit is set and the busy bit is cleared.

Initiating a serial EEPROM read or write operation when the BUSY bit is set produces undefined results.

SMBus errors may occur when accessing the serial EEPROM. If an error occurs, then it is reported in the

SMBus Status (SMBUSSTS) register. Software should check for errors before and after each serial

EEPROM access.

PES48H12G2 utilizes external SMBus/I2C-bus I/O expanders connected to the master SMBus interface

for hot-plug and port status signals. PES48H12G2 is designed to work with Phillips PCA9555 compatible I/

O expanders (i.e., PCA9555, PCA9535, and PCA9539). See the Phillips PCA9555 data sheet for details on

the operation of this device. An external SMBus I/O expander provides 16 bit I/O pins that may be config-

ured as inputs or outputs.

- Set RSTHALT bit in SWCTL register

- ICSERR bit is set in the SMBUSSTS register