Table 8.1 Serdes Transmit Level Controls In The S[X]Txlctl0 And S[X]Txlctl1 Registers - Renesas IDT 89HPES48H12G2 User Manual

IDT SerDes
Notes
PES48H12G2 User Manual
PHY Operation Mode
Voltage Data De-
Swing Rate emphasis
Full-Swing 2.5 GT/s -3.5 dB
Full-Swing 5.0 GT/s -3.5 dB
Full-Swing 5.0 GT/s -6.0 dB
Low-Swing 2.5 GT/s 0 dB
Low-Swing 5.0 GT/s 0 dB

Table 8.1 SerDes Transmit Level Controls in the S[x]TXLCTL0 and S[x]TXLCTL1 Registers

As shown in Table 8.1, there are six parameters that may be programmed to adjust the transmitter drive
levels. These are:
– Coarse Slew Rate Control (in the S[x]TXLCTL0 register).
– Transmitter Equalization Control (in the S[x]TXLCTL0 register).
– Fine Slew Rate Control (in the S[x]TXLCTL0 register).
– Coarse De-emphasis Control (in the S[x]TXLCTL0 register).
– Fine De-emphasis Control (in the S[x]TXLCTL1 register).
– Drive Level Control (in the S[x]TXLCTL1 register).
Modification of these settings take an immediate effect on the SerDes. Therefore, the link does not need
to be retrained explicitly (i.e., by setting the link-retrain (LRET) bit in the PCIELCTL) in order for these
settings to take effect. Still, the user must be careful when changing the transmit voltage margin while the
port is in normal operating mode, as this may result in the link instability.
Table 8.2 shows a number of possible settings for the drive, de-emphasis, and slew rate controls in
1
Gen1 mode . These can be used as guidance when adjusting the SerDes transmit levels. The default
setting is highlighted. Note that in Gen1 mode, de-emphasis is ideally -3.5dB with +/- 0.5dB error (refer to
Section 4.3.3.5 of the PCI Express 2.0 Specification). All settings listed in the table ensure that the de-
emphasis is kept within the allowable range.
1.
Table values are based on simulations using the Snowbush SerDes HSPICE model and device package s-
parameters. Values are sampled at the device pins. The simulation assumes typical conditions, with VddPEA =
VddPETA = 1.0V, VddPEHA = 2.5V, and TX_AMPBOOST = 0x1. Please refer to the device data sheet for post-
silicon device characterization data.
Relevant fields in
S[x]TXLCTL0
Coarse De-
emphasis Slew Rate
Control & Control
Transmitter (Course & Fine)
Equalization
CDC_FS3DBG1 TX_SLEW_G1 &
TX_EQ_3DBG1 TX_FSLEW_G1
CDC_FS3DBG2 TX_SLEW_G2 &
TX_EQ_3DBG2 TX_FSLEWG2
CDC_FS6DBG2
TX_EQ_6DBG2
N/A TX_SLEW_G1 &
TX_FSLEW_G1
N/A TX_SLEW_G2 &
TX_FSLEW_G2
8 - 5
Relevant fields in
S[x]TXLCTL1
Drive Level / Fine-De-
emphasis Control
TDVL_FS3DBG1 /
FDC_FS3DBG1
TDVL_FS3DBG2 /
FDC_FS3DBG2
TDVL_FS6DBG2 /
FDC_FS6DBG2
TDVL_LSG1
TDVL_LSG2
April 5, 2013