Table of Contents
Advertisement
IDT SMBus Interfaces
Notes
PES48H12G2 User Manual
I/O Expander 8
SMBus I/O
Expander
Type
Bit
1
0 (I/O-0.0)
I
1 (I/O-0.1)
I
2 (I/O-0.2)
I
3 (I/O-0.3)
I
4 (I/O-0.4)
I
5 (I/O-0.5)
I
6 (I/O-0.6)
I
7 (I/O-0.7)
I
8 (I/O-1.0)
I
9 (I/O-1.1)
I
10 (I/O-1.2)
I
11 (I/O-1.3)
I
12 (I/O-1.4)
I
13 (I/O-1.5)
I
14 (I/O-1.6)
I
15 (I/O-1.7)
I
1.
I/O-x.y corresponds to the notation used for PCA9555 port x I/O pin y.
I/O Expander 9
SMBus I/O
Expander
Type
Bit
1
0 (I/O-0.0)
I
1 (I/O-0.1)
I
2 (I/O-0.2)
I
Table 13.7 Pin Mapping I/O Expander 9 (Part 1 of 2)
Signal
P0MRLN
Port 0 manually operated retention latch (MRL)
input
P1MRLN
Port 1 manually operated retention latch (MRL)
input
P2MRLN
Port 2 manually operated retention latch (MRL)
input
P3MRLN
Port 3 manually operated retention latch (MRL)
input
P4MRLN
Port 4 manually operated retention latch (MRL)
input
P5MRLN
Port 5 manually operated retention latch (MRL)
input
P6MRLN
Port 6 manually operated retention latch (MRL)
input
P7MRLN
Port 7 manually operated retention latch (MRL)
input
P8MRLN
Port 8 manually operated retention latch (MRL)
input
P9MRLN
Port 9 manually operated retention latch (MRL)
input
Unused
Unused
P12MRLN
Port 12 manually operated retention latch (MRL)
input
P13MRLN
Port 13 manually operated retention latch (MRL)
input
Unused
Unused
Table 13.6 Pin Mapping I/O Expander 8
Signal
P0ILOCKST
Port 0 electromechanical interlock state input
P1ILOCKST
Port 1 electromechanical interlock state input
P2ILOCKST
Port 2 electromechanical interlock state input
13 - 10
Description
Description
April 5, 2013
Advertisement
Table of Contents
