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IDT Clocking
Notes
PES48H12G2 User Manual
Figure 4.5 Clocking Connection for a Port in Local Port Clocked Mode, in a Non-Common Clocked Configuration
Modification of a Port's Clock Mode
The clocking mode associated with a port may be modified at any time, with the only requirement being
that the reference clock that will be used by the port after the port's clocking mode is modified must be
stable prior to the modification.
– Modifying a port's clocking mode causes the PHY to transition to the Detect state. This is not
considered a surprise link down event.
– If the clock mode change requires a modification of the reference clock associated with the port's
SerDes, the SerDes is re-initialized
– If the port is not in disabled mode, the PHY retrains the link.
Modifying a port's clock mode is subject to the following restrictions regarding the clock frequencies.
Initial Port
Clock Mode as
Determined by
the CLKMODE
Pins
Global Clocked Mode
Local Port Clocked Mode
Table 4.5 Clock Frequency Limitations When Modifying a Port's Clock Mode
Switch
GCLK
Clock
Generator
PxCLK
Clock
Generator
Clock
Link Partner
Generator
Subsequent Port
Clock Mode
Change by
Programming
the PCLKMODE
Register
Local Port Clocked Mode If the GCLK operates at a nominal frequency of
100 Mhz, the port's PxCLK must also operate at
a nominal frequency of 100 Mhz.
If the GCLK operates at a nominal frequency of
125 Mhz, the port's PxCLK must also operate at
a nominal frequency of 125 Mhz.
Per the rules outlined in section Spread Spec-
trum Clocking (SSC) Support on page 4-2, this
port mode change is only allowed when the
GCLK does not have SSC. Still, the PxCLK is
allowed to have an SSC component on top of
the frequencies described above.
Global Clocked Mode
This port clock mode change is only allowed if
the global clock (GCLK) frequency is 100 Mhz
(i.e., as selected by the GCLKFSEL pin).
4 - 6
Port
Limitations / Caveats
April 5, 2013
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