Renesas IDT 89HPES8T5 IO Expansion Switch Manuals

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Renesas IDT 89HPES8T5 User Manual (171 pages)

PCI Express Switch

Brand: Renesas | Category: Switch | Size: 2 MB

About this Manual
3
Content Summary
3
Signal Nomenclature
3
Numeric Representations
4
Data Units
4
Register Terminology
5
Use of Hypertext
6
Reference Documents
6
Revision History
6
Table of Contents
7
PES8T5 Device Overview
19
Introduction
19
List of Features
19
System Diagrams
21
Table 1.1 Table
21
Logic Diagram
22
Figure 1.3 PES8T5 Logic Diagram
22
System Identification
23
Vendor ID
23
Device ID
23
Revision ID
23
Jtag ID
23
Ssid/Ssvid
23
Device Serial Number Enhanced Capability
23
Pin Description
24
Table 1.3 PCI Express Interface Pins
24
Table 1.4 Smbus Interface Pins
24
Table 1.5 General Purpose I/O Pins
25
Table 1.6 System Pins
26
Table 1.7 Test Pins
27
Table 1.8 Power and Ground Pins
27
Pin Characteristics
28
Table 1.9 Pin Characteristics
28
Clocking, Reset, and Initialization
31
Introduction
31
Table 2.1 Reference Clock Mode Encoding
31
Figure 2.1 Common Clock on Upstream and Downstream
31
Figure 2.2 Non-Common Clock on Upstream; Common Clock on Downstream (Must Disable Spread Spectrum Clock)
32
Figure 2.3 Common Clock on Upstream; Non-Common Clock on Downstream (Must Disable Spread Spectrum Clock)
32
Table 2.2 Boot Configuration Vector Signals
33
Figure 2.4 Non-Common Clock on Upstream and Downstream
33
Reset
34
Fundamental Reset
34
Hot Reset
36
Figure 2.5 Fundamental Reset in Transparent Mode with Serial EEPROM Initialization
36
Upstream Secondary Bus Reset
37
Downstream Secondary Bus Reset
38
Downstream Port Reset Outputs
38
Power Enable Controlled Reset Output
39
Power Good Controlled Reset Output
39
Figure 2.6 Power Enable Controlled Reset Output Mode Operation
39
Figure 2.7 Power Good Controlled Reset Output Mode Operation
39
Theory of Operation
41
Introduction
41
Table 3.1 IFB Buffer Sizes
41
Data Paths
42
Store-And-Forward Vs. Cut-Through Switching and Latency
42
Table 3.2 PES8T5 Buffer Sizes
42
Table 3.3 Bus Decoupler Queue and Insertion Buffer Size
42
Switch Core
43
Table 3.4 Latency
43
Figure 3.1 Simplified Switch Core U-Bus and D-Bus Datapath
43
Transaction Routing
44
Transaction Reordering
44
Table 3.5 Switch Routing Methods
44
Scheduling and Port Arbitration
45
Table 3.6 IFB Transaction Ordering
45
Figure 3.2 U-Bus Arbitration
47
Peer-To-Peer Transactions
48
Bus Locking
48
Port Interrupts
50
Legacy Interrupt Emulation
50
Table 3.7 Downstream Port Interrupts
50
Standard Pcie Error Detection and Handling
51
Physical Layer Errors
51
Data Link Layer Errors
51
Table 3.8 PES8T5 Downstream to Upstream Port Interrupt Routing
51
Table 3.9 Physical Layer Errors
51
Transaction Layer Errors
52
Table 3.10 Data Link Layer Errors
52
Table 3.11 Transaction Layer Errors
52
Table 3.12 Ingress Malformed TLP Error Checks
53
Routing Errors
54
Table 3.13 Egress Malformed TLP Error Checks
54
Switch Specific Error Detection and Handling
55
Switch Time-Outs
55
End-To-End Parity Checking
56
TLP Processing
57
Link Operation
59
Introduction
59
Polarity Inversion
59
Link Width Negotiation
59
Lane Reversal
59
Link Retraining
60
Figure 4.1 Port Lane Reversal for Maximum Link Width of X4 (Maxlnkwdth[5:0]=0X4)
60
Figure 4.2 Port Lane Reversal for Maximum Link Width of X2 (Maxlnkwdth[5:0]=0X2)
60
Link down
61
Slot Power Limit Support
61
Upstream Port
61
Downstream Port
61
Link States
61
Active State Power Management
62
Figure 4.3 PES8T5 ASPM Link Sate Transitions
62
Link Status
63
General Purpose I/O
65
Introduction
65
GPIO Configuration
65
Table 5.1 General Purpose I/O Pin Alternate Function
65
Table 5.2 GPIO Pin Configuration
65
GPIO Pin Configured as an Input
66
GPIO Pin Configured as an Output
66
GPIO Pin Configured as an Alternate Function
66
Smbus Interfaces
67
Introduction
67
Figure 6.1 Smbus Interface Configuration Examples
67
Master Smbus Interface
68
Initialization
68
Serial EEPROM
68
Table 6.1 Serial EEPROM Smbus Address
68
Table 6.2 PES8T5 Compatible Serial Eeproms
69
Figure 6.2 Single Double Word Initialization Sequence Format
69
Figure 6.3 Sequential Double Word Initialization Sequence Format
70
Figure 6.4 Configuration Done Sequence Format
70
Table 6.3 Serial EEPROM Initialization Errors
71
I/O Expanders
72
Table 6.4 I/O Expander Function Allocation
72
Table 6.5 I/O Expander 0 Signals
75
Table 6.6 I/O Expander 1 Signals
76
Table 6.7 I/O Expander 2 Signals
76
Slave Smbus Interface
77
Table 6.8 I/O Expander 4 Signals
77
Initialization
78
Smbus Transactions
78
Table 6.9 Slave Smbus Address When a Static Address Is Selected
78
Figure 6.5 Slave Smbus Command Code Format
78
Table 6.10 Slave Smbus Command Code Fields
79
Table 6.11 CSR Register Read or Write Operation Byte Sequence
80
Table 6.12 CSR Register Read or Write CMD Field Description
80
Figure 6.6 CSR Register Read or Write CMD Field Format
80
Table 6.13 Serial EEPROM Read or Write Operation Byte Sequence
81
Table 6.14 Serial EEPROM Read or Write CMD Field Description
82
Figure 6.7 Serial EEPROM Read or Write CMD Field Format
82
Figure 6.8 CSR Register Read Using Smbus Block Write/Read Transactions with PEC
83
Figure 6.9 Serial EEPROM Read Using Smbus Block Write/Read Transactions with PEC
83
Figure 6.10 CSR Register Write Using Smbus Block Write Transactions with PEC Disabled
83
Figure 6.11 Serial EEPROM Write Using Smbus Block Write Transactions with PEC Disabled
84
Figure 6.12 Serial EEPROM Write Using Smbus Block Write Transactions with PEC Enabled
84
Figure 6.13 CSR Register Read Using Smbus Read and Write Transactions with PEC Disabled
85
Power Management
87
Introduction
87
Figure 7.1 PES8T5 Power Management State Transition Diagram
87
PME Messages
88
Power Express Power Management Fence Protocol
88
Table 7.1 PES8T5 Power Management State Transition Diagram
88
Power Budgeting Capability
89
Hot-Plug and Hot-Swap
91
Introduction
91
Figure 8.1 Hot-Plug on Switch Downstream Slots Application
91
Figure 8.2 Hot-Plug with Switch on Add-In Card Application
92
Figure 8.3 Hot-Plug with Carrier Card Application
92
Table 8.1 Downstream Port Hot-Plug Signals
93
Hot-Plug I/O Expander
94
Hot-Plug Interrupts and Wake-Up
94
Legacy System Hot-Plug Support
94
Figure 8.4 PES8T5 Hot-Plug Event Signalling
95
Hot-Swap
96
Configuration Registers
97
Introduction
97
Table 9.1 Base Addresses for Port Configuration Space Registers
97
Figure 9.1 Port Configuration Space Organization
98
Upstream Port (Port 0)
99
Table 9.2 Upstream Port 0 Configuration Space Registers
99
Downstream Ports (Ports 2 through 5)
104
Table 9.3 Downstream Ports 2 through 5 Configuration Space Registers
104
Register Definitions
108
Type 1 Configuration Header Registers
108
PCI Express Capability Structure
117
Power Management Capability Structure
129
Message Signaled Interrupt Capability Structure
131
Subsystem ID and Subsystem Vendor ID
132
Extended Configuration Space Access Registers
133
Advanced Error Reporting (AER) Enhanced Capability
133
Device Serial Number Enhanced Capability
139
PCI Express Virtual Channel Capability
140
Power Budgeting Enhanced Capability
145
Switch Control and Status Registers
146
Internal Switch Error Control and Status Registers
158
JTAG Boundary Scan
163
Introduction
163
Test Access Point
163
Signal Definitions
163
Figure 10.1 Diagram of the JTAG Logic
163
Table 10.1 JTAG Pin Descriptions
164
Figure 10.2 State Diagram of Pes8T5'S TAP Controller
164
Boundary Scan Chain
165
Table 10.2 Boundary Scan Chain
165
Test Data Register (DR)
166
Boundary Scan Registers
166
Figure 10.3 Diagram of Observe-Only Input Cell
166
Figure 10.4 Diagram of Output Cell
167
Figure 10.5 Diagram of Bidirectional Cell
167
Instruction Register (IR)
168
Extest
168
Table 10.3 Instructions Supported by Pes8T5'S JTAG Boundary Scan
168
Sample/Preload
169
Bypass
169
Clamp
169
Idcode
169
Table 10.4 System Controller Device Identification Register
169
Figure 10.6 Device ID Register Format
169
Validate
170
Reserved
170
Usage Considerations
170

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Renesas IDT 89HPES8T5 User Manual (171 pages)

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