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IDT Theory of Operation
Notes
PES48H12G2 User Manual
Address Routed TLPs
TLPs received by an upstream port that match the upstream port's address range but which do not
match a downstream port's address range within the partition (i.e., TLPs that do not route through the parti-
tion).
TLPs received by a downstream port that do not match the address range of any other downstream port
within the partition, but match the address range of the partition's upstream port. TLPs received by a down-
stream port whose address decoding indicates they are to route back to the port on which they were
received, if ACS Upstream Forwarding is disabled on the port. When ACS Upstream Forwarding is
enabled, such TLPs are not considered errors and are forwarded upstream.
TLPs received by the primary side of a port that is not enabled for such transactions.
– For prefetchable memory and non-prefetchable memory transactions the Memory Access Enable
(MAE) bit must be set in the port's PCI Command (PCICMD) register.
– For I/O transactions the I/O Access Enable (IOAE) bit must be set in the port's PCI Command
(PCICMD) register.
MEM or IO TLPs received on a downstream port and the port's Bus Master Enable (BME) bit in the
PCICMD register is cleared. MEM or IO TLPs from downstream ports that target the upstream port and the
Bus Master Enable (BME) bit is cleared in the upstream port's PCICMD register. A VGA route from a VGA
enabled downstream port.
Configuration Requests (Routed by ID)
Type 0 requests that arrive on a downstream port. Type 1 requests that arrive on a downstream port.
Type 1 requests that do not route through the upstream port's PCI-to-PCI bridge. Type 1 requests that
are converted to Type 0 requests at the upstream port but which do not target an enabled downstream port
device number (i.e., target a PCI-to-PCI bridge device number that doesn't exist.
Type 1 requests that route through the PES48H12G2, target a downstream port's link partner (i.e., are
converted to a Type 0 request at the downstream port), and which do not target device zero. Note that this
check is disabled when the Alternative Routing ID (ARI) function is enabled via the ARIFEN bit in the
PCIEDCTL2 register.
Completions (Routed by ID)
Completions that attempt to route back onto the link on which they were received are silently dropped, if
ACS Upstream Forwarding is disabled. When ACS Upstream Forwarding is enabled, such completion
TLPs are not dropped and are forwarded upstream. Completions that do not have a valid route through the
PES48H12G2 are silently dropped. All completions that terminate within the PES48H12G2 (i.e., ones that
target the upstream switch port bus number or any device/function on the virtual PCI bus within the switch)
are treated as unexpected completions.
ID Routed Messages
Messages that attempt to route back onto the link on which they were received, if ACS Upstream
Forwarding is disabled. When ACS Upstream Forwarding is enabled, such TLPs are not considered errors
and are forwarded upstream. Messages that do not have a valid route through the PES48H12G2.
Messages that target a downstream port device number that does not exist.
A non-Vendor Defined Type 1 message which targets an enabled PES48H12G2 port. Vendor Defined
Type 1 messages received by a PES48H12G2 port are silently discarded.
A non-Vendor Defined Type 1 message which is received by the upstream port.
Bus Locking
The PES48H12G2 supports locked transactions, allowing legacy software to run without modification on
PCIe. Locked transactions are only supported between an upstream switch port (i.e., PCI-to-PCI bridge
function) and a downstream port in the same partition. Only one locked transaction sequence may be in
progress at a time.
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April 5, 2013
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