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IDT Hot-Plug and Hot-Swap
Notes
PES48H12G2 User Manual
Following a partition hot-reset, a partition upstream secondary bus hot-reset, or a downstream
secondary bus hot-reset, each downstream port's PHY will transition the link to the Hot-Reset state and
subsequently re-train the link starting from the Detect state. When this occurs, the Hot-Plug controller for
the port does not set the Presence Detect Changed (PDC) bit in the PCIESSTS register.
Port Reset Outputs
Individual port reset outputs PxRSTN are provided as I/O expander outputs.
Port reset outputs may be configured to operate in one of two modes. These modes are power enable
controlled reset output and power good controlled reset output. The port reset output mode for all ports is
determined by the Reset Mode (RSTMODE) field in the Hot-Plug Configuration Control (HPCFGCTL)
register.
In addition to a port reset output being asserted as determined by the Reset Mode (RSTMODE) field, a
port reset output is also asserted under the following circumstances.
– When the partition with which the port is associated experiences a partition fundamental reset.
See section Partition Fundamental Reset on page 5-8 for more information on partition funda-
mental resets.
– When the operating mode of a port is modified and the OMA field is set to reset. See section Reset
Mode Change Behavior on page 6-14 for more information on what occurs when the OMA field is
set to reset.
Hardware ensures that the minimum port reset output assertion pulse width is no less than 200 µS.
Power Enable Controlled Reset Output
In this mode a downstream port reset output state is controlled as a side effect of slot power being
turned on or off. The operation of this mode is illustrated in Figure 10.4. A downstream port's slot power is
controlled by the Power Controller Control (PCC) bit in the PCI Express Slot Control (PCIESCTL) register
PxPEP
PxRSTN
Figure 10.4 Power Enable Controlled Reset Output Mode Operation
While slot power is disabled, the corresponding downstream port reset output is asserted.
When slot power is enabled by writing a zero to the PCC bit, the Port x Power Enable Output (PxPEP) is
asserted and then power to the slot is enabled and the corresponding downstream port reset output is
negated. The time between the assertion of the PxPEP signal and the negation of the PxRSTN signal is
controlled by the value in the Slot Power to Reset Negation (PWR2RST) field in the HPCFGCTL register.
While slot power is enabled, the corresponding downstream port reset output is negated.
When slot power is disabled by writing a one to the PCC bit, the corresponding downstream port reset
output is asserted and then slot power is disabled. The time between the assertion of the PxRSTN signal
and the negation of the PxPEP signal is controlled by the value in the Reset Negation to Slot Power
(RST2PWR) field in the HPCFGCTL register.
Power Good Controlled Reset Output
As in the Power Enable Controlled Reset mode, in this mode a downstream port reset output state is
controlled as a side effect of slot power being turned on or off. However, the timing in this mode depends on
the power good state of the slot's power supply. The operation of this mode is illustrated in Figure 10.5.
T
PWR2RST
10 - 5
T
RST2PWR
April 5, 2013
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