Register Terminology - Renesas IDT 89HPES48H12G2 User Manual

Pci express switch
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IDT
Notes
PES48H12G2 User Manual
Term
Byte
Word
Doubleword (Dword)
Quadword (Qword)
In quadwords, bit 63 is always the most significant bit and bit 0 is the least significant bit. In double-
words, bit 31 is always the most significant bit and bit 0 is the least significant bit. In words, bit 15 is always
the most significant bit and bit 0 is the least significant bit. In bytes, bit 7 is always the most significant bit
and bit 0 is the least significant bit.
The ordering of bytes within words is referred to as either "big endian" or "little endian." Big endian
systems label byte zero as the most significant (leftmost) byte of a word. Little endian systems label byte
zero as the least significant (rightmost) byte of a word. See Figure 2.
Figure 2 Example of Byte Ordering for "Big Endian" or "Little Endian" System Definition

Register Terminology

Software in the context of this register terminology refers to modifications made by PCIe root configura-
tion writes, writes to registers made through the slave SMBus interface, or serial EEPROM register initial-
ization. See Table 2.
Words
Bytes
1/2
1
2
4
Table 1 Data Unit Terminology
bit 31
bit 0
0
1
2
3
Address of Bytes within Words: Big Endian
bit 31
bit 0
3
2
1
0
Address of Bytes within Words: Little Endian
3
Bits
1
8
2
16
4
32
8
64
April 5, 2013

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