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IDT PES48H12G2 Device Overview
Logic Diagram
Global
Reference Clocks
PCI Express
Switch
SerDes Input
Port 0
PCI Express
Switch
SerDes Input
Port 1
PCI Express
Switch
SerDes Input
Port 2
PCI Express
Switch
SerDes Input
Port 3
PCI Express
Switch
SerDes Input
Port 9
PCI Express
Switch
SerDes Input
Port 12
PCI Express
Switch
SerDes Input
Port 13
Master
SMBus Interface
Slave
SMBus Interface
System
Pins
PES48H12G2 User Manual
GCLKN[1:0]
GCLKP[1:0]
GCLKFSEL
P0CLKN
PE00RP[3:0]
PE00RN[3:0]
PE01RP[3:0]
PE01RN[3:0]
P2CLKN
PE02RP[3:0]
PE02RN[3:0]
PE03RP[3:0]
PE03RN[3:0]
PE09RP[3:0]
PE09RN[3:0]
PE12RP[3:0]
PE12RN[3:0]
PES48H12G2
PE13RP[3:0]
PE13RN[3:0]
MSMBCLK
MSMBDAT
2
SSMBADDR[2,1]
SSMBCLK
SSMBDAT
3
CLKMODE[2:0]
RSTHALT
PERSTN
4
SWMODE[3:0]
P01MERGEN
P23MERGEN
P45MERGEN
P67MERGEN
P89MERGEN
P1213MERGEN
Figure 1.2 PES48H12G2 Logic Diagram
1 - 5
PCI Express
Switch
PE00TP[3:0]
SerDes Output
PE00TN[3:0]
Port 0
PCI Express
Switch
PE09TP[3:0]
SerDes Output
PE09TN[3:0]
Port 9
PCI Express
PE12TP[3:0]
Switch
PE12TN[3:0]
SerDes Output
Port 12
PCI Express
PE13TP[3:0]
Switch
PE13TN[3:0]
SerDes Output
Port 13
General Purpose
9
GPIO[8:0]
I/O
JTAG_TCK
JTAG_TDI
JTAG Pins
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
SerDes
REFRES[11:0]
Reference
REFRESPLL
Resistors
V
CORE
DD
V
I/O
DD
V
PEA
DD
Power/Ground
V
PEHA
DD
V
SS
V
PETA
DD
April 5, 2013
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