Arbitration; Table 3.4 Packet Ordering Rules In The Pes48H12G2 - Renesas IDT 89HPES48H12G2 User Manual

IDT Switch Core
Notes
PES48H12G2 User Manual
Row Pass Column?
Posted Memory
Request Write or
Message
Request
Non Posted Read
Request Request
IO or Config-
uration Write
Request
Completion Read Com-
Request pletion
IO or Config-
uration Write
Completion

Table 3.4 Packet Ordering Rules in the PES48H12G2

Arbitration

Packets stored in the ingress buffers are subject to arbitration as they are moved towards the egress
port. The switch core performs all packet arbitration functions in the switch. Architecturally, arbitration is
done at the egress ports. Each port has a dedicated arbitration configuration as programmed in the port's
VC Capability Structure.
Packets undergo two levels of arbitration at an egress port:
– Port arbitration within a VC
– VC arbitration for access to the egress link
Figure 3.2 shows the architectural model of arbitration. The following sub-sections describe arbitration in
detail.
Posted
Non-Posted Request
Request
Memory
Configur
Write or Read
Message Request
Request
Request
No Yes
No No
No No
'Yes' if packet Yes
has RO bit
set; Else 'No'
Yes
3 - 5
Completion
IO or
IO or
Configur
Read
ation
ation Comple-
Write
Write tion
Comple-
Yes Yes
No Yes
No Yes
Yes No
Yes No
April 5, 2013
tion
Yes
Yes
Yes
No
No