Table 13.17 Serial Eeprom Read Or Write Cmd Field Description; Figure 13.7 Serial Eeprom Read Or Write Cmd Field Format; Figure 13.8 Csr Register Read Using Smbus Block Write/Read Transactions With Pec Disabled - Renesas IDT 89HPES48H12G2 User Manual

IDT SMBus Interfaces
Notes
PES48H12G2 User Manual
Bit Bit
7 6
0

Figure 13.7 Serial EEPROM Read or Write CMD Field Format

Bit
Name Type
Field
0 OP
1 USA
2 Reserved
3 NAERR RW1C
4 Reserved
5 OTHERERR RW1C
7:6 Reserved

Table 13.17 Serial EEPROM Read or Write CMD Field Description

Sample Slave SMBus Operation
This section illustrates sample Slave SMBus operations. Shaded items are driven by PES48H12G2's
slave SMBus interface and non-shaded items are driven by an SMBus host.
PES48H12G2 Slave CCODE
S Wr A
SMBus Address START,END
PES48H12G2 Slave CCODE
S Wr A
SMBus Address START,END
PES48H12G2 Slave CCODE
S Wr A
SMBus Address START,END
A
ADDRU DATALL

Figure 13.8 CSR Register Read Using SMBus Block Write/Read Transactions with PEC Disabled

Bit Bit Bit
5 4 3
OTHERERR 0 NAERR
RW Serial EEPROM Operation. This field encodes the serial EEPROM
operation to be performed.
0 - Serial EEPROM write
1 - Serial EEPROM read
RW Use Specified Address. When this bit is set, the serial EEPROM
SMBus address specified in the EEADDR is used instead of that
specified in the MSMBADDR field in the SMBUSSTS register.
Reserved field.
No Acknowledge Error. This bit is set if an unexpected NACK is
observed during a master SMBus transaction when accessing the
serial EEPROM. This bit has the same function as the NAERR bit in
the SMBUSSTS register.
The setting of this bit may indicate the following: that the addressed
device does not exist on the SMBus (i.e., addressing error), data is
unavailable or the device is busy, an invalid command was detected
by the slave, invalid data was detected by the slave.
Reserved field.
Other Error. This bit is set if a misplaced START or STOP condition
is detected by the master SMBus interface when accessing the serial
EEPROM. This bit has the same function as the OTHERERR bit in
the SMBUSSTS register.
0 Reserved field. Must be zero.
A A
BYTCNT=3 CMD=read
(PES48H12G2 not ready with data)
N
P
PES48H12G2 Slave
A S Rd A BYTCNT=7
SMBus Address
A A
DATALM DATAUM
13 - 18
Bit Bit Bit
2 1 0
0 USA OP
Description
A A
ADDRL ADDRU
A CMD (status) A ADDRL
A N P
DATAUU
April 5, 2013
A P
A