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IDT Reset and Initialization
Notes
PES48H12G2 User Manual
– All registers associated with the port remain accessible from the global address space.
– The port remains in this state regardless of the setting of the port's operating mode (i.e., via the
port's SWPORTxCTL register).
An active port behaves as described throughout the rest of this specification and may be configured in
one of several operating modes, as described in Chapter 6, Switch Partitions.
Partition Resets
A partition reset is a reset that is associated with a specific switch partition. The reset has an effect only
on those functions and switch ports associated with that switch partition. It has no effect on the operation of
other switch partitions, ports in other switch partitions, or logic not associated with a switch partition (e.g.,
Master SMBus).
A partition reset may be subdivided into four subcategories: partition fundamental reset, partition hot
reset, partition upstream secondary bus reset, and partition downstream secondary bus reset. These
subcategories correspond to resets defined by the PCI architecture.
– A partition fundamental reset logically causes all logic associated with a partition to take on its
initial state, but does not cause the state of register fields denoted as SWSticky to be modified.
– A partition hot reset logically causes all logic to be returned to an initial state, but does not cause
the state of register fields denoted as Sticky or SWSticky to be modified.
– An partition upstream secondary bus reset logically causes all devices on the virtual PCI bus of a
partition to be hot reset except the upstream port (i.e., upstream PCI-to-PCI bridge).
– A partition downstream secondary bus reset causes a hot reset to be propagated on the corre-
sponding external link.
The operation of the slave SMBus interface is unaffected by a partition reset. Using the slave SMBus to
access a register that is in the process of being reset causes the register's default value to be returned on a
read and written data to be ignored on writes.
Partition Fundamental Reset
A partition fundamental reset is initiated by any of the following events.
– A switch fundamental reset.
– Assertion of a partition fundamental reset signal.
– As directed by the Switch Partition State (STATE) field in the Switch Partition (SWPARTxCTL)
register.
Associated with each partition is a partition fundamental reset input (PARTxPERSTN).
– The partition fundamental reset input for the first four partitions (i.e., partitions zero through three)
are available as GPIO alternate functions.
– The partition fundamental reset input for all partitions are available on external I/O expanders.
When a partition fundamental reset is initiated, the following sequence of actions take place.
1.
All logic associated with the switch partition (i.e., switch ports, switch core, etc.) is logically
reset to its initial state.
2.
All port links associated with the partition enter the 'Detect' state.
3.
All registers and fields, except those designated as SWSticky, take on their initial value. The
value of SWSticky registers and field is preserved across a partition fundamental reset.
4.
As long as the condition that initiated the partition fundamental reset persists (e.g., the
fundamental reset signal is asserted or the STATE field remains set to reset), logic associ-
ated with the partition remains at this step.
5.
Ports associated with the partition begin to link train and normal partition operation begins.
1.
Refer to Chapter 15, Register Organization, for details on the switch's global address space.
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April 5, 2013
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