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IDT Link Operation
Notes
PES48H12G2 User Manual
Hot Reset Operation on a Crosslink
When a PES48H12G2 port forms a crosslink, hot reset operates as follows.
– For a port operating in downstream switch port mode:
• Regardless of the physical layer's mode of operation (i.e., upstream or downstream lanes), the
physical layer responds to the reception of training sets with the hot reset bit set by transitioning
to the hot reset state as specified in the PCI Express Base Specification. The hot reset does not
reset the configuration registers of the port and does not affect other ports in the partition.
• If the port's physical layer operates as 'downstream lanes' and a higher layer directs the port to
the hot reset state (e.g., partition hot reset, upstream secondary hot reset, downstream
secondary hot reset), the physical layer enters the recovery state and proceeds to the hot reset
state, as specified in the PCI Express Base Specification.
• If the port's physical layer operates as 'upstream lanes', the PES48H12G2 provides no higher
layer mechanism to direct the physical layer to enter the hot reset state. This implies that in a
crosslink formed by a PES48H12G2 downstream port whose physical layer has trained as
'upstream lanes', hot reset across the link may only be propagated by the link partner's port
(which must have trained as a downstream port with downstream lanes).
– For a port operating in upstream switch port mode:
• There is no higher layer mechanism to place the port in hot reset state.
• Regardless of the physical layer's mode of operation (i.e., upstream or downstream lanes), the
physical layer responds to the reception of training sets with the hot reset bit set by transitioning
to the hot reset state. The hot reset has the effect described in section Partition Hot Reset on
page 5-9.
Link Disable Operation on a Crosslink
When a port is crosslinked, link disable operates as follows.
– For a port operating in downstream switch port mode:
• Regardless of the port's physical layer mode of operation (i.e., downstream lanes or upstream
lanes):
If a higher layer directs the port to disable the link (i.e., the Link Disable (LDIS) bit is set in
the port's PCIELCTL register), the physical layer enters the recovery state and proceeds
to the disabled state, as specified in the PCI Express Base Specification.
The physical layer responds to the reception of training sets with the disabled bit set by
transitioning to the disabled state as specified in the PCI Express Base Specification.
– For a port operating in upstream switch port mode:
• There is no higher layer mechanism to place the port's link in the disabled state.
• Regardless of the port's physical layer mode of operation (i.e., downstream lanes or upstream
lanes), the physical layer responds to the reception of training sets with the disabled bit set by
transitioning to the disabled state as specified in the PCI Express Base Specification.
Gen1 Compatibility Mode
The PES48H12G2 ports may be configured to operate in 'Gen1 Compatibility Mode'. The intent of this
mode is to overcome interoperability problems that arise when PCI Express 2.0 devices link train with
devices that conform to the PCIe 1.1 or earlier specifications (a.k.a., Gen1 devices). Specifically, this mode
overcomes the problem in which Gen1 devices react incorrectly to newly defined bits in the PCI Express 2.0
specification for the PHY training sets. Such bits include bits 2, 6, and 7 in symbol four of the TS1 and TS2
training sets.
A PES48H12G2 port is placed in Gen1 Compatibility Mode by setting the Gen1 Compatibility Mode
Enable (G1CME) bit in the PHYLCFG0 register and fully retraining the link (i.e., via the FLRET bit the
PHYLSTATE0 register).
1.
Note that a port that is placed in the disabled operating mode (see section Switch Ports on page 6-4) does not
place its physical layer in the disabled state, but rather transitions the physical layer directly to the detect state.
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1
April 5, 2013
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