Table 1.10 Power, Ground, And Serdes Resistor Pins - Renesas IDT 89HPES48H12G2 User Manual

IDT PES48H12G2 Device Overview
Notes
PES48H12G2 User Manual
Signal Type
JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
Signal Type
REFRES[11:0] I/O External Reference Resistors. Provides a reference for the SerDes bias
currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor should be
connected from these pins to ground.
REFRESPLL I/O PLL External Reference Resistor. Provides a reference for the PLL bias
currents and PLL calibration circuitry. A 3K Ohm +/- 1% resistor should be
connected from this pin to ground.
V CORE I Core V
DD
V I/O I I/O V
DD
V PEA I PCI Express Analog Power. Serdes analog power supply (1.0V).
DD
V PEHA I PCI Express Analog High Power. Serdes analog power supply (2.5V).
DD
V PETA I PCI Express Transmitter Analog Voltage. Serdes transmitter analog
DD
power supply (1.0V).
V I Ground.
SS

Table 1.10 Power, Ground, and SerDes Resistor Pins

1 - 12
Name/Description
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Table 1.9 Test Pins (Part 2 of 2)
Name/Description
Power supply for core logic (1.0V).
DD.
LVTTL I/O buffer power supply (2.5V or preferred 3.3V).
DD.
April 5, 2013