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IDT PES48H12G2 Device Overview
Notes
PES48H12G2 User Manual
Signal
Type
PE07TP[3:0]
O
PCI Express Port 7 Serial Data Transmit. Differential PCI Express trans-
PE07TN[3:0]
mit pairs for port 7. When port 6 is merged with port 7, these signals
become port 6 transmit pairs for lanes 4 through 7.
PE08RP[3:0]
I
PCI Express Port 8 Serial Data Receive. Differential PCI Express receive
PE08RN[3:0]
pairs for port 8.
PE08TP[3:0]
O
PCI Express Port 8 Serial Data Transmit. Differential PCI Express trans-
PE08TN[3:0]
mit pairs for port 8.
PE09RP[3:0]
I
PCI Express Port 9 Serial Data Receive. Differential PCI Express receive
PE09RN[3:0]
pairs for port 9. When port 8 is merged with port 9, these signals become
port 8 receive pairs for lanes 4 through 7.
PE09TP[3:0]
O
PCI Express Port 9 Serial Data Transmit. Differential PCI Express trans-
PE09TN[3:0]
mit pairs for port 9. When port 8 is merged with port 9, these signals
become port 8 transmit pairs for lanes 4 through 7.
PE12RP[3:0]
I
PCI Express Port 12 Serial Data Receive. Differential PCI Express
PE12RN[3:0]
receive pairs for port 12.
PE12TP[3:0]
O
PCI Express Port 12 Serial Data Transmit. Differential PCI Express
PE12TN[3:0]
transmit pairs for port 12.
PE13RP[3:0]
I
PCI Express Port 13 Serial Data Receive. Differential PCI Express
PE13RN[3:0]
receive pairs for port 13. When port 12 is merged with port 13, these sig-
nals become port 12 receive pairs for lanes 4 through 7.
PE13TP[3:0]
O
PCI Express Port 13 Serial Data Transmit. Differential PCI Express
PE13TN[3:0]
transmit pairs for port 13. When port 12 is merged with port 13, these sig-
nals become port 12 transmit pairs for lanes 4 through 7.
Table 1.4 PCI Express Interface Pins (Part 2 of 2)
Signal
Type
GCLKN[1:0]
I
Global Reference Clock. Differential reference clock input pair. This clock
GCLKP[1:0]
is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic. The frequency of the differential reference
clock is determined by the GCLKFSEL signal.
P[2,0]CLKN
I
Port Reference Clock. Differential reference clock pair associated with
P[2,0]CLKP
ports 0 and 2.
port clocked mode. Refer to Chapter 4 for further details.
1.
Unused port clock pins should be connected to Vss on the board.
Signal
Type
MSMBCLK
I/O
Master SMBus Clock. This bidirectional signal is used to synchronize
transfers on the master SMBus.
MSMBDAT
I/O
Master SMBus Data. This bidirectional signal is used for data on the mas-
ter SMBus.
Table 1.6 SMBus Interface Pins (Part 1 of 2)
1 - 8
Name/Description
Name/Description
1
To be used when the corresponding port operates in local
Table 1.5 Reference Clock Pins
Name/Description
April 5, 2013
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