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IDT Switch Partitions
Notes
PES48H12G2 User Manual
– Change the port operating mode by setting the following fields in the SWPORTxCTL register. This
causes the port to be added to the selected partition.
• MODE field to 'Downstream switch port'
• PART field to the appropriate partition (e.g., 0 or 1)
• OMA field to 'no action'.
– Do a full link retrain on the port by setting the FLRET bit in the port's PHYLSTATE0 register. This
will cause the port's link to retrain from the Detect state.
5. Add the upstream port to each partition using the following sequence for each port.
– Change the port operating mode by setting the following fields in the SWPORTxCTL register. This
causes the port to be added to the selected partition.
• MODE field to 'Upstream switch port'
• PART field to the appropriate partition (e.g., 0 or 1)
• OMA field to 'no action'.
6. Disable the unused ports by using the following sequence for each port.
– Change the port operating mode by setting the following fields in the SWPORTxCTL register. This
causes the port to be disabled.
• MODE field to 'Disabled'
• OMA field to 'no action'.
• PART field to any value (this field is irrelevant for this port operating mode change).
7. Set the PCI Express capabilities and extended capabilities list for the upstream ports. This is done
by configuring the Next Pointer (NXTPTR) field appropriately in the capability header register of the
capabilities that form the two lists. Refer to section Capability Structures on page 15-3 for details.
This step is not required for the downstream ports.
– Specifically, the following register fields must be set appropriately.
• NXTPTR field in the PCI Power Management Capabilities (PMCAP) register
• NXTPTR field in the PCI Express VC Extended Capability Header (PCIEVCCAP) register
8.
If the application requires partition reset control via the PARTxPERSTN input signal, enable the
appropriate GPIO alternate function as described in Chapter 12.
9. Set the following timer registers to their default values.
– Side Effect Delay Timer (SEDELAY register)
– Port Operating Mode Change Drain Delay Timer (POMCDELAY register)
– Reset Drain Delay Timer (RDRAINDELAY register)
– Upstream Secondary Bus Reset Delay (USSBRDELAY register)
The above sequence must complete before the PCI Express hierarchy is enumerated (i.e., in less than 1
second from the de-assertion of the switch fundamental reset signal (PERSTNT)). Refer to section Switch
Fundamental Reset on page 5-3 for details regarding switch fundamental reset timings.
Dynamic Reconfiguration
Dynamic reconfiguration refers to the reconfiguration of the switch partitions after the switch funda-
mental reset sequence completes (i.e., run-time reconfiguration). Possible partition reconfigurations are list
below:
– A downstream port is added or removed from a partition
– An upstream port is added or removed from a partition
– The operating mode of the upstream port is modified.
Dynamic partition reconfiguration is subject to the restrictions described in section Partition State
Change via Other Methods on page 6-4 and section Port Operating Mode Change via Other Methods on
page 6-8. Partition reconfiguration may be initiated by software through modification of the operating mode
of a port.
6 - 16
April 5, 2013
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