Proprietary Port Specific Registers; Port Control And Status Registers - Renesas IDT 89HPES48H12G2 User Manual

IDT PCI to PCI Bridge and Proprietary Port Specific Registers

Proprietary Port Specific Registers

Port Control and Status Registers

PCIESCTLIV - PCI Express Slot Control Initial Value (0x420)
Bit
Field Name
0
1
2 MRLSCE
3
PES48H12G2 User Manual
Field Default
Type
Value
ABPE RW 0x0
SWSticky
PFDE RW 0x0
SWSticky
RW 0x0
SWSticky
PDCE RW 0x0
SWSticky
Description
Attention Button Pressed Enable.
This field contains the initial value of the corresponding field in the
PCI Express Slot Control (PCIESCTL) register when the corre-
sponding slot or hot-plug capability is enabled.
A partition reset does not reset slot and hot-plug capability bits
since they are RWL. The intent of this field is to allow the initial
value of the corresponding field in the PCIESCTL register to be
controlled following a partition fundamental reset.
A write to this field causes an immediate effect in the correspond-
ing field in the PCIESCTL register.
Power Fault Detected Enable.
This field contains the initial value of the corresponding field in the
PCI Express Slot Control (PCIESCTL) register when the corre-
sponding slot or hot-plug capability is enabled.
A partition reset does not reset slot and hot-plug capability bits
since they are RWL. The intent of this field is to allow the initial
value of the corresponding field in the PCIESCTL register to be
controlled following a partition fundamental reset.
A write to this field causes an immediate effect in the correspond-
ing field in the PCIESCTL register.
MRL Sensor Change Enable.
This field contains the initial value of the corresponding field in the
PCI Express Slot Control (PCIESCTL) register when the corre-
sponding slot or hot-plug capability is enabled.
A partition reset does not reset slot and hot-plug capability bits
since they are RWL. The intent of this field is to allow the initial
value of the corresponding field in the PCIESCTL register to be
controlled following a partition fundamental reset.
A write to this field causes an immediate effect in the correspond-
ing field in the PCIESCTL register.
Presence Detected Changed Enable.
This field contains the initial value of the corresponding field in the
PCI Express Slot Control (PCIESCTL) register when the corre-
sponding slot or hot-plug capability is enabled.
A partition reset does not reset slot and hot-plug capability bits
since they are RWL. The intent of this field is to allow the initial
value of the corresponding field in the PCIESCTL register to be
controlled following a partition fundamental reset.
A write to this field causes an immediate effect in the correspond-
ing field in the PCIESCTL register.
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