Internal Error Control And Status Registers - Renesas IDT 89HPES48H12G2 User Manual

IDT PCI to PCI Bridge and Proprietary Port Specific Registers
Bit
Field Name
11 Reserved
12 DLLLASCE
15:13 Reserved

Internal Error Control and Status Registers

IERRORCTL - Internal Error Reporting Control (0x480)
Bit
Field Name
0 IERROREN
31:1 Reserved
IERRORSTS - Internal Error Reporting Status (0x484)
Bit
Field Name
0 IFBPTLPTO
1 IFBNPTLPTO
2 IFBCPTLPTO
3 Reserved
4 EFBPTLPTO
5 EFBNPTLPTO
6 EFBCPTLPTO
7 IFBDATSBE
PES48H12G2 User Manual
Field Default
Type
Value
RO 0x0
RW 0x0
SWSticky
RO 0x0
Field Default
Type
Value
RW 0x1
SWSticky
RO 0x0
Field Default
Type
Value
RW1C 0x0
SWSticky
RW1C 0x0
SWSticky
RW1C 0x0
SWSticky
RO 0x0
RW1C 0x0
SWSticky
RW1C 0x0
SWSticky
RW1C 0x0
SWSticky
RW1C 0x0
SWSticky
Description
Reserved field.
Data Link Layer Link Active State Change Enable.
This field contains the initial value of the corresponding field in the
PCI Express Slot Control (PCIESCTL) register when the corre-
sponding slot or hot-plug capability is enabled.
A partition reset does not reset slot and hot-plug capability bits
since they are RWL. The intent of this field is to allow the initial
value of the corresponding field in the PCIESCTL register to be
controlled following a partition fundamental reset.
A write to this field causes an immediate effect in the correspond-
ing field in the PCIESCTL register.
Reserved field.
Description
Internal Error Reporting Enable. When this bit is set, internal
error reporting is enabled and reported through AER. Refer to sec-
tion Internal Errors on page 3-13 for details.
Reserved field.
Description
IFB Posted TLP Time-Out. This bit is set when a posted TLP
time-out is detected in the IFB.
IFB Non-Posted TLP Time-Out. This bit is set when a non-posted
TLP time-out is detected in the IFB.
IFB Completion TLP Time-Out. This bit is set when a completion
time-out is detected in the IFB.
Reserved field.
EFB Posted TLP Time-Out. This bit is set when a posted TLP
time-out is detected in the EFB.
EFB Non-Posted TLP Time-Out. This bit is set when a non-
posted TLP time-out is detected in the EFB.
EFB Completion TLP Time-Out. This bit is set when a completion
time-out is detected in the EFB.
IFB Data Single Bit Error. This bit is set when a single bit ECC
error is detected and corrected in the IFB data RAM.
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