Hot-Swap - Renesas IDT 89HPES48H12G2 User Manual

IDT Hot-Plug and Hot-Swap
Notes
PES48H12G2 User Manual
Slot Control
Register
Hot-Plug Interrupt
Enable
Slot Status
Register
RW
Command
Completed Enable
Command
Completed
RW
RW1C RW1C
Attention Button
Pressed Enable
Attention Button
Pressed
RW
RW1C RW1C
Power Fault
Detected Enable
Power Fault
Detected
RW
RW1C RW1C
MRL Sensor State
Changed Enable
MRL Sensor State
Changed
RW
RW1C RW1C
Presence Detected
Changed Enable
Presence Detected
Changed
RW
RW1C RW1C
Data Link Layer
State Changed Enable
Data Link Layer
State Changed
RW
RW1C RW1C
Figure 10.6 PES48H12G2 Hot-Plug Event Signalling

Hot-Swap

PES48H12G2 is hot-swap capable and meets the following requirements
– All of the I/Os are tri-stated on reset (i.e., SerDes, GPIO, SMBuses, etc.)
– All I/O cells function predictably from early power. This means that the device is able to tolerate a
non-monotonic ramp-up as well as a rapid ramp-up of the DC power.
– All I/O cells are able to tolerate a precharge voltage
– Since no clock is present during physical connection, the device will maintain all outputs in a high-
impedance state even when no clock is present.
– The I/O cells meet VI requirements for hot-swap.
– The I/O cells respect the required leakage current limits over the entire input voltage range.
In summary, PES48H12G2 meets all of the I/O requirements necessary to build a PICMG compliant hot-
swap board or system. The hot-swap I/O buffers of PES48H12G2 may also be used to construct proprietary
hot-swap systems. See the PES48H12G2 Data Sheet for a detailed specification of I/O buffer characteris-
tics.
PME Enable
10 - 8
General Purpose Event
Enable
RW
General Purpose
Event Mechanism
Interrupt
Disable
RW
Activate INTx
Mechanism
Activate MSI
Mechanism
RW
MSI Enable
Bit
Bit
RW
Activate Wakeup
Mechanism
April 5, 2013