Renesas IDT Tsi576 Manuals

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Renesas IDT Tsi576 User Manual

Renesas IDT Tsi576 User Manual (530 pages)

Brand: Renesas | Category: Switch | Size: 3 MB

Table of Contents

Table of Contents
3
About this Document
17
Scope
17
Document Conventions
17
Revision History
18
Functional Overview
21
Overview
21
Typical Applications
22
Figure 1: Block Diagram
22
Figure 2: Wireless Baseband Card
23
Figure 3: Video Infrastructure Card
23
Features
24
Serial Rapidio Interface
26
Features
26
Transaction Flow Overview
26
Maintenance Requests
27
Control Symbols
27
Multicast Engine
27
Multicast Operation
27
Features
27
Serial Rapidio Electrical Interface
28
Figure 4: Tsi576 MAC Block Diagram
29
Internal Switching Fabric (ISF)
30
Internal Register Bus (AHB)
30
I 2 C Interface
30
JTAG Interface
32
Serial Rapidio Interface
35
Overview
35
Features
35
Transaction Flow Overview
36
Maintenance Requests
36
Control Symbols
36
Transaction Flow
37
Lookup Tables
37
Filling the Lookup Tables
38
Figure 5: LUT Mode of Operation
39
LUT Modes
40
Flat Mode
40
Figure 6: Flat Mode Routing
41
Figure 7: Flat Mode Routing Example
42
Figure 8: Flat Mode LUT Configuration Example
43
Hierarchical Mode
45
Figure 9: Hierarchical Mode
46
Figure 10: Hierarchical Mode Routing Example
47
Mixed Mode of Operation
49
Lookup Table Parity
49
Lookup Table Error Summary
50
Table 1: Error Summary
50
Lookup Table Entry States
51
Table 2: Lookup Table States
51
Maintenance Packets
53
Table 3: Examples of Maintenance Packets with Hop Count = 0 and Associated Tsi576 Responses
53
Multicast Event Control Symbols
55
MCS Reception
55
Generating an MCS
56
Restrictions
56
Reset Control Symbol Processing
57
Data Integrity Checking
57
Packet Data Integrity Checking
57
Control Symbol Data Integrity Checking
57
Error Management
57
Software Assisted Error Recovery
58
Hot Insertion and Hot Extraction
59
Hot Insertion
60
Hot Extraction
61
Hot Extraction System Notification
62
Loss of Lane Synchronization
62
Figure 11: LOLS Silent Period
63
Dead Link Timer
64
Lane Sync Timer
64
Serial Rapidio Electrical Interface
65
Overview
65
Figure 12: Tsi576 MAC Block Diagram
66
Port Numbering
67
Table 4: Tsi576 Port Numbering
67
Port Configuration
68
Port Aggregation: 1X and 4X Modes
68
Figure 13: Port Configuration
68
1X + 1X Configuration
69
Configuration
70
Clocking
70
Changing the Clock Speed
71
Table 5: Reference Clock Frequency and Supported Serial Rapidio Data Rates
71
Changing the Clock Speed through I
72
Port Power down
72
Default Configurations on Power down
73
Special Conditions for Port 0 Power down
73
Power-Down Options
74
Configuration and Operation through Power-Down
74
Table 6: Serial Port Power-Down Procedure
74
Port Lanes
75
Lane Synchronization and Alignment
75
Lane Swapping
76
Table 7: Lane Sequence
76
Programmable Transmit and Receive Equalization
77
Transmit Drive Level and Equalization
77
Receive Equalization
78
Figure 14: Drive Strength and Equalization Waveform
78
Port Loopback Testing
79
Figure 15: Tsi576 Loopbacks
79
Digital Equipment Loopback
80
Logical Line Loopback
80
Bit Error Rate Testing (BERT)
80
BERT Pattern Generator
80
Table 8: Patterns Supported by Generator
80
BERT Pattern Matcher and Error Counter
82
Fixed Pattern-Based BERT
82
Table 9: Patterns Supported by Matcher
82
Using PRBS Scripts for the Transmitters and Receivers
83
Internal Switching Fabric
85
Overview
85
Functional Behavior
86
Figure 16: ISF Block Diagram
86
Transfer Modes
87
Arbitration for Egress Port
88
Strict Priority Arbitration
88
Figure 17: Egress Arbitration: Weighted Round Robin and Strict Priority
88
Weighted Round Robin (WRR) Arbitration
89
Figure 18: Weighted Round Robin Arbiter Per Priority Group
89
Table 10: Sample Register Settings for WRR in a Given Priority Group (WRR_EN=1)
90
Packet Queuing
91
Output Queuing on the Egress Port
91
Figure 19: Ingress and Egress Packet Queues in Tsi576
91
Table 11: Examples of Use of Watermarks
93
Input Queue for the ISF Port
94
Input Arbitration
95
Input Queuing Model for the Multicast Work Queue
99
Input Queuing Model for the Broadcast Buffer
100
Output Queuing Model for Multicast
100
ISF Bandwidth
100
Multicast
103
Overview
103
Multicast Operation
103
Features
103
Multicast Operation with Multiple Tsi57X Switches
104
Figure 20: Multicast Operation - Option 1
104
Multicast Terminology
105
Figure 21: Multicast Operation - Option 2
105
Table 12: Multicast Terminology
105
Multicast Behavior Overview
106
Multicast Work Queue
107
Broadcast Buffers
107
Figure 22: Multicast Packet Flow in the Tsi576
108
Multicast Group Tables
110
Configuring Basic Associations
112
Figure 23: Relationship Representation
112
Configuring Multicast Masks
113
Figure 24: Completed Tables at the End of Configuration
114
Configuring Multicast Masks Using the IDT Specific Registers
116
Figure 25: IDT-Specific Multicast Mask Configuration
117
Arbitration for Multicast Engine Ingress Port
118
Figure 26: Tundra-Specific Multicast Mask Configuration
118
Figure 27: Arbitration Algorithm for Multicast Port
119
Figure 28: Arbitration Algorithm for Multicast Port
119
Error Management of Multicast Packets
120
Packet TEA
120
Multicast Packet Stomping
120
Multicast Maximum Latency Timer
120
Silent Discard of Packets
121
Port-Writes and Multicast
122
Port Reset
122
Event Notification
123
Overview
123
Event Summary
124
Table 13: Tsi576 Events
124
Error Rate Thresholds
128
Maintaining Packet Flow
129
Error Stopped State Recovery
130
Error Stopped States
130
Link Error Clearing and Recovery
131
Figure 29: Control Symbol Format
132
Event Capture
133
Table 14: Error Rate Error Events
134
Port-Write Notifications
135
Destination ID
136
Payload
136
Servicing Port-Writes
137
Table 15: Port Write Packet Data Payload - Error Reporting
137
Port-Writes and Hot Insertion/Hot Extraction Notification
138
Port-Writes and Multicast
138
Interrupt Notifications
138
Figure 30: Rapidio Block Interrupt and Port Write Hierarchy
139
Int_B Signal
140
Global Interrupt Status Register and Interrupt Handling
140
Table 16: Port X Error and Status Register Status
141
Interrupt Notification and Port-Writes
142
Reset Control Symbol and Interrupt Handling
142
I 2 C Interface
143
Overview
143
Protocol Overview
145
Block Diagram
146
Figure 31: I 2 C Block Diagram
147
Figure 32: I 2 C Reference Diagram
148
Tsi576 as I 2 C Master
149
Figure 33: Software-Initiated Master Transactions
150
Example EEPROM Read and Write
151
Master Clock Generation
151
Master Bus Arbitration
152
Master External Device Addressing
152
Master Peripheral Addressing
152
Master Data Transactions
153
Tsi576 as I 2 C Slave
153
Slave Clock Stretching
155
Figure 34: Transaction Protocols for Tsi576 as Slave
155
Slave Device Addressing
156
Slave Peripheral Addressing
156
External I C Register Map
157
Slave Write Data Transactions
158
Slave Read Data Transactions
159
Slave Internal Register Accesses
159
Slave Access Examples
160
Resetting the I 2 C Slave Interface
163
Mailboxes
163
Figure 35: I 2 C Mailbox Operation
164
Table 17: Externally Visible I
164
Incoming Mailbox
165
Outgoing Mailbox
165
Smbus Support
165
Unsupported Smbus Features
166
Smbus Protocol Support
166
Figure 36: Smbus Protocol Support
167
Smbus Alert Response Protocol Support
168
Boot Load Sequence
168
Figure 37: Smbus Alert Response Protocol
168
Figure 38: Boot Load Sequence
169
Idle Detect
170
EEPROM Reset Sequence
170
Wait for Bus Idle
170
EEPROM Device Detection
171
Loading Register Data from EEPROM
171
Chaining
172
EEPROM Data Format
172
Table 18: Format for Boot Loadable EEPROM
173
Table 19: Sample EEPROM Loading Two Registers
173
I2C Boot Time
174
Table 20: Sample EEPROM with Chaining
174
Accelerating Boot Load
175
Error Handling
176
Table 21: I 2 C Error Handling
176
Interrupt Handling
178
Figure 39: I 2 C Interrupt Generation
178
Events Versus Interrupts
179
Figure 40: I 2 C Event and Interrupt Logic
180
Timeouts
181
Table 22: I 2 C Interrupt to Events Mapping
181
Figure 41: I 2 C Timeout Periods
184
Bus Timing
185
Figure 42: I 2 C Bus Timing Diagrams
186
Start/Restart Condition Setup and Hold
187
Stop Condition Setup
187
I2C_SD Setup and Hold
187
I2C_SCLK Nominal and Minimum Periods
188
Idle Detect Period
188
Performance
189
Overview
189
Throughput
189
Latency
189
Performance Monitoring
190
Figure 43: Latency Illustration
190
Table 23: Performance Monitoring Parameters
191
Traffic Efficiency
192
Throughput
192
Bottleneck Detection
193
Congestion Detection
193
Resetting Performance Registers
193
Configuring the Tsi576 for Performance Measurements
194
Clock Speeds
194
Tsi576 ISF Arbitration Settings
194
Tsi576 Rapidio Transmission Scheduler Settings
195
Tsi576 Rapidio Buffer Watermark Selection Settings
195
Port-To-Port Performance Characteristics
195
Port-To-Port Packet Latency Performance
195
Packet Throughput Performance
196
Table 24: 4X/1X Latency Numbers under no Congestion
196
Multicast Performance
197
Congestion Detection and Management
198
Table 25: 4X/1X Multicast Latency Numbers under no Congestion
198
Figure 44: Congestion and Detection Flowchart
199
Congestion Registers
200
Figure 45: Congestion Example
202
JTAG Interface
203
Overview
203
JTAG Device Identification Number
204
JTAG Register Access Details
204
Format
204
Figure 46: Register Access from JTAG - Serial Data in
204
Figure 47: Register Access from JTAG - Serial Data out
204
Write Access to Registers from the JTAG Interface
205
Read Access to Registers from the JTAG Interface
205
Clocks, Resets and Power-Up Options
207
Clocks
207
Clocking Architecture
208
Figure 48: Tsi576 Clocking Architecture
208
Serdes Clocks
209
Reference Clocks
209
Table 26: Tsi576 Input Reference Clocks
209
Clock Domains
210
Clock Gating
210
Table 27: Tsi576 Clock Domains
210
Resets
211
Device Reset
211
Per-Port Reset
213
Generating a Rapidio Reset Request to a Peer Device
213
JTAG Reset
213
Power-Up Options
214
Power-Up Option Signals
214
Table 28: Power-Up Options Signals
215
Default Port Speed
216
Port Power-Up and Power-Down
216
Port Width Override
216
Signals
217
Overview
217
Table 29: Signal Types
217
Endian Ordering
218
Port Numbering
218
Table 30: Tsi576 Port Numbering
218
Signal Groupings
219
Figure 49: Signal Groupings
220
Table 31: Tsi576 Signal Descriptions
221
Pinlist and Ballmap
229
Serial Rapidio Registers
231
Overview
231
Table 32: Address Rules
231
Reserved Register Addresses and Fields
232
Table 33: Register Access Types
232
Port Numbering
233
Table 34: Tsi576 Port Numbering
233
Conventions
234
Register Map
235
Table 35: Register Map Overview
235
Table 36: Register Map
236
Rapidio Logical Layer and Transport Layer Registers
247
Rapidio Device Identity CAR
248
Rapidio Device Information CAR
249
Rapidio Assembly Identity CAR
250
Rapidio Assembly Information CAR
251
Rapidio Processing Element Features CAR
252
Rapidio Switch Port Information CAR
254
Rapidio Source Operation CAR
255
Rapidio Switch Multicast Support CAR
257
Rapidio Route LUT Size CAR
258
Rapidio Switch Multicast Information CAR
259
Rapidio Host Base Device ID Lock CSR
260
Rapidio Component Tag CSR
261
Rapidio Route Configuration Destid CSR
262
Rapidio Route Configuration Output Port CSR
263
Rapidio Route LUT Attributes (Default Port) CSR
264
Rapidio Multicast Mask Configuration Register
265
Rapidio Multicast Destid Configuration Register
267
Rapidio Multicast Destid Association Register
268
Rapidio Physical Layer Registers
270
Table 37: Physical Interface Register Offsets
270
Rapidio 1X or 4X Switch Port Maintenance Block Header
272
Rapidio Switch Port Link Timeout Control CSR
273
Rapidio Switch Port General Control CSR
274
Rapidio Serial Port X Link Maintenance Request CSR
275
Rapidio Serial Port X Link Maintenance Response CSR
277
Rapidio Serial Port X Local Ackid Status CSR
278
Rapidio Port X Error and Status CSR
280
Rapidio Serial Port X Control CSR
283
Rapidio Error Management Extension Registers
287
Table 38: Error Management Registers
287
Port Behavior When Error Rate Failed Threshold Is Reached
288
Table 39: STOP_FAIL_EN and DROP_EN Setting
288
Rapidio Error Reporting Block Header
289
Rapidio Logical and Transport Layer Error Detect CSR
290
Rapidio Logical and Transport Layer Error Enable CSR
291
Rapidio Logical and Transport Layer Address Capture CSR
292
Rapidio Logical and Transport Layer Device ID Capture CSR
293
Rapidio Logical and Transport Layer Control Capture CSR
294
Rapidio Port-Write Target Device ID CSR
295
Rapidio Port X Error Detect CSR
296
Rapidio Port X Error Rate Enable CSR
299
Rapidio Port X Error Capture Attributes CSR and Debug 0
301
Table 40: ERR_TYPE Values
301
Rapidio Port X Packet and Control Symbol Error Capture CSR 0 and Debug 1
303
Rapidio Port X Packet Error Capture CSR 1 and Debug 2
304
Rapidio Port X Packet Error Capture CSR 2 and Debug 3
304
Rapidio Port X Packet Error Capture CSR 3 and Debug 4
305
Rapidio Port X Error Rate CSR
306
Rapidio Port X Error Rate Threshold CSR
308
IDT-Specific Rapidio Registers
309
Table 41: Tundra-Specific Broadcast Rapidio Registers
309
Table 42: Tundra-Specific Per-Port Performance Registers
310
Rapidio Port X Discovery Timer
311
Rapidio Port X Mode CSR
312
Rapidio Port X Multicast-Event Control Symbol and Reset Control Symbol Interrupt CSR
314
Rapidio Port X Rapidio Watermarks
315
Rapidio Port X Route Config Destid CSR
316
Rapidio Port X Route Config Output Port CSR
317
Rapidio Port X Local Routing LUT Base CSR
318
Rapidio Multicast Write ID X Register
319
Rapidio Multicast Write Mask X Register
320
Rapidio Port X Control Independent Register
321
Rapidio Port X Send Multicast-Event Control Symbol Register
324
Rapidio Port X LUT Parity Error Info CSR
325
Rapidio Port X Control Symbol Transmit
327
Rapidio Port X Interrupt Status Register
328
Rapidio Port X Interrupt Generate Register
331
IDT-Specific Performance Registers
333
Table 43: Tundra-Specific Per-Port Performance Registers
333
Rapidio Port X Performance Statistics Counter 0 and 1 Control Register
334
Rapidio Port X Performance Statistics Counter 2 and 3 Control Register
338
Rapidio Port X Performance Statistics Counter 4 and 5 Control Register
342
Rapidio Port X Performance Statistics Counter 0 Register
346
Rapidio Port X Performance Statistics Counter 1 Register
347
Rapidio Port X Performance Statistics Counter 2 Register
348
Rapidio Port X Performance Statistics Counter 3 Register
349
Rapidio Port X Performance Statistics Counter 4 Register
350
Rapidio Port X Performance Statistics Counter 5 Register
351
Rapidio Port X Transmitter Output Queue Depth Threshold Register
352
Rapidio Port X Transmitter Output Queue Congestion Status Register
354
Rapidio Port X Transmitter Output Queue Congestion Period Register
356
Rapidio Port X Receiver Input Queue Depth Threshold Register
357
Rapidio Port X Receiver Input Queue Congestion Status Register
359
Rapidio Port X Receiver Input Queue Congestion Period Register
361
Rapidio Port X Reordering Counter Register
362
Serial Port Electrical Layer Registers
363
Table 44: Tundra-Specific Rapidio Registers
363
BYPASS_INIT Functionality
364
Table 45: Serial Port Electrical Layer Registers
364
SRIO MAC X Serdes Configuration Channel 0
365
SRIO MAC X Serdes Configuration Channel 1
368
SRIO MAC X Serdes Configuration Channel 2
370
SRIO MAC X Serdes Configuration Channel 3
372
SRIO MAC X Serdes Configuration Global
374
Table 46: TX_LVL Values
375
Table 47: AC JTAG Level Programmed by ACJT_LVL[4:0]
376
SRIO MAC X Serdes Configuration Globalb
378
SRIO MAC X Digital Loopback and Clock Selection Register
379
Internal Switching Fabric (ISF) Registers
382
Fabric Control Register
382
Fabric Interrupt Status Register
384
Rapidio Broadcast Buffer Maximum Latency Expired Error Register
386
Rapidio Broadcast Buffer Maximum Latency Expired Override
388
Utility Unit Registers
390
Global Interrupt Status Register
390
Global Interrupt Enable Register
392
Rapidio Port-Write Timeout Control Register
394
Rapidio Port Write Outstanding Request Register
395
MCES Pin Control Register
396
Multicast Registers
397
Rapidio Multicast Register Version CSR
397
Rapidio Multicast Maximum Latency Counter CSR
398
Rapidio Port X ISF Watermarks
399
Port X Prefer Unicast and Multicast Packet Prio 0 Register
400
Port X Prefer Unicast and Multicast Packet Prio 1 Register
401
Port X Prefer Unicast and Multicast Packet Prio 2 Register
402
Port X Prefer Unicast and Multicast Packet Prio 3 Register
403
Serdes Per Lane Register
404
Table 48: Serdes Register Map
404
Serdes Lane 0 Pattern Generator Control Register
405
Serdes Lane 1 Pattern Generator Control Register
406
Serdes Lane 2 Pattern Generator Control Register
407
Serdes Lane 3 Pattern Generator Control Register
408
Serdes Lane 0 Pattern Matcher Control Register
409
Serdes Lane 1 Pattern Matcher Control Register
410
Serdes Lane 2 Pattern Matcher Control Register
411
Serdes Lane 3 Pattern Matcher Control Register
412
Serdes Lane 0 Frequency and Phase Value Register
413
Serdes Lane 1 Frequency and Phase Value Register
414
Serdes Lane 2 Frequency and Phase Value Register
415
Serdes Lane 3 Frequency and Phase Value Register
416
I2C Registers
417
Register Map
417
Table 49: I 2 C Register Map
417
Register Descriptions
420
I 2 C Device ID Register
420
I 2 C Reset Register
421
I 2 C Master Configuration Register
422
I 2 C Master Control Register
424
Table 50: Master Operation Sequence
426
I 2 C Master Receive Data Register
427
I 2 C Master Transmit Data Register
428
I 2 C Access Status Register
429
I 2 C Interrupt Status Register
432
I 2 C Interrupt Enable Register
435
I 2 C Interrupt Set Register
437
I 2 C Slave Configuration Register
439
I 2 C Boot Control Register
442
Externally Visible I C Internal Write Address Register
446
Externally Visible I C Internal Write Data Register
447
Externally Visible I C Internal Read Address Register
448
Externally Visible I
448
Internal Read Data Register
449
Externally Visible I
449
Slave Access Status Register
450
Externally Visible I C Internal Access Control Register
452
Externally Visible I
452
Status Register
454
Externally Visible I
454
Enable Register
458
Externally Visible I C Outgoing Mailbox Register
462
Externally Visible I C Incoming Mailbox Register
463
I 2 C Event and Event Snapshot Registers
464
I 2 C New Event Register
468
I 2 C Enable Event Register
471
I 2 C Time Period Divider Register
474
I 2 C Start Condition Setup/Hold Timing Register
475
I 2 C Stop/Idle Timing Register
476
I2C_SD Setup and Hold Timing Register
477
I2C_SCLK High and Low Timing Register
478
I2C_SCLK Minimum High and Low Timing Register
479
I2C_SCLK Low and Arbitration Timeout Register
480
I 2 C Byte/Transaction Timeout Register
481
I 2 C Boot and Diagnostic Timer
482
I 2 C Boot Load Diagnostic Progress Register
483
I 2 C Boot Load Diagnostic Configuration Register
484
Serial Rapidio Protocol Overview
485
Protocol
485
Packets
485
Control Symbols
486
Physical Layer
486
PCS Layer
486
PMA Layer
486
Physical Protocol
486
Table 51: Special Characters and Encoding
487
Table 52: Control Symbol Construction
488
Clocking
491
Line Rate Support
491
Table 53: Tsi576 Supported Line Rates
491
Register Requirements Using 125 Mhz S_CLK for a 3.125 Gbps Link Rate
492
P_CLK Programming
495
Rapidio Specifications Directly Affected by Changes in the P_CLK Frequency
495
Table 54: Timer Values with P_CLK and TVAL Variations
496
Table 55: Timer Values with DISCOVERY_TIMER and P_CLK Variations
497
IDT Specific Timers
498
Table 56: Timer Values with P_CLK and DLT_THRESH Variations
498
I 2 C Interface and Timers
499
Other Performance Factors
505
PRBS Scripts
507
Tsi576_Start_Prbs_All.txt Script
507
Tsi576_Framer_Disable.txt Script
509
Tsi576_Sync_Prbs_All.txt Script
510
Tsi576_Read_Prbs_All.txt Script
513
EEPROM Scripts
517
Script
517
Index
525

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