Clocking, Reset, And Initialization; Introduction; Initialization; Figure 2.1 Common Clock On Upstream And Downstream - Renesas IDT 89HPES4T4 User Manual

Notes
PES4T4 User Manual
®

Introduction

The PES4T4 has a differential reference clock input that is used internally to generate all of the clocks
required by the internal switch logic and the SerDes. The frequency of the reference clock is 100MHz. The
reference clock differential inputs feeds several on-chip PLLs. Each PLL generates a 2.5 GHz clock which
is used by several SerDes lanes and produces a 250 MHz core clock.
Clock Operation
When the CCLKUS and CCLKDS pins are asserted, they indicate that a common clock is being used
between the upstream device and the upstream port, as well as between the downstream devices and the
downstream ports. The Spread Spectrum Clock (SSC) must be disabled when the non-common clock is
used on either the upstream port or downstream port. Figures 2.1 through 2.4 illustrate the operation of the
CCLKUS and CCLKDS clocks using a common clock and a non-common clock.
Root Complex
Hi
Clock Generator
Figure 2.1 Common Clock on Upstream and Downstream (option to enable or disable Spread Spectrum Clock)
Clocking, Reset, and
PES4T4
Port 0
CCLKUS
PEREFCLK
2 - 1
Chapter 2

Initialization

Port 2
EP
EP
Port 4
CCLKDS
Hi
February 1, 2011