Configuration Registers; Table 9.1 Base Addresses For Port Configuration Space Registers - Renesas IDT 89HPES4T4 User Manual

Notes
PES4T4 User Manual
®
Configuration Space Organization
Each software visible register in the PES4T4 is contained in the PCI configuration space of one of the
ports. Thus, there are no registers in the PES4T4 that cannot be accessed by the root. Each software
visible register in the PES4T4 has a system address. The system address is formed by adding the PCI
configuration space offset value of the register to the base address of the port in which it is located. The
system address is used for serial EEPROM register initialization.
The base address for each PES4T4 port is listed in Table 9.1. The PCI configuration space offset
addresses for registers in the upstream port are listed in Table 9.2 while the PCI configuration space offset
addresses for registers in downstream ports are listed Table 9.3.
Base
Address
0x0000
0x2000
0x3000
0x4000

Table 9.1 Base Addresses for Port Configuration Space Registers

As shown in Figure 9.1, upstream and downstream ports share a similar PCI configuration space
register layout. The upstream port contains global switch control and status registers. The downstream
ports contain an MSI capability structure to generate MSIs as a result of hot-plug events, and the upstream
port supports MSI capability structure to report internal parity errors.
Reading from an upstream port offset not defined in Table 9.2 or a downstream offset not defined in
Table 9.3 returns a value of zero. Writes to such an offset complete successfully but modify no data and
have no other effect.

Configuration Registers

PCI Configuration Space
Port 0 configuration space (upstream port)
Port 2 configuration space (downstream port)
Port 3 configuration space (downstream port)
Port 4 configuration space (downstream port)
9 - 1
Chapter 9
February 1, 2011