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IDT Clocking, Reset, and Initialization
Notes
PES4T4 User Manual
When a hot reset occurs, the following sequence is executed.
1.
Each downstream port whose link is up propagates the hot reset by transmitting TS1 ordered sets
with the hot reset bit set.
2.
All of the logic associated with the PES4T4 is reset except the PLLs, SerDes, and master SMBus
interface.
3. All registers fields in all registers, except those denoted as "sticky" or Read and Write when Unlocked
(i.e, RWL), are reset to their initial value. The value of fields denoted as "sticky" or RWL is preserved
across a hot reset.
4. Link training begins. While link training is in progress, proceed to step 5.
5. The PCI Express stacks and associated logic are held in a quasi-reset state in which the following
actions occur.
All links enter an active link training state within 20ms of the clearing of the hot reset condition.
Within 100 ms of the clearing of the fundamental reset condition, all of the stacks are able to
process configuration transactions and respond to these transactions with a configuration
request retry status completion. All other transactions are ignored.
6. If the selected switch operating mode is one that requires initialization from the serial EEPROM and
the Disable Hot Reset Serial EEPROM Initialization (DHRSTSEI) bit is not set in the Switch Control
(SWCTL) register, then the contents of the serial EEPROM are read and the appropriate PES4T4
registers are updated.
If a one is written by the serial EEPROM to the Full Link Retrain (FLRET) bit in the Phy Link
State 0 (PHYLSTATE0) register, then link retraining is initiated on the corresponding port using
the current link parameters.
If an error is detected during loading of the serial EEPROM, then loading of the serial EEPROM
is aborted and the RSTHALT bit is set in the SWCTL register. Error information is recorded in
the SMBUSSTS register.
When serial EEPROM initialization completes or when an error is detected, the DONE bit in the
SMBUSSTS register is set.
7. If the Reset Halt (RSTHALT) bit is set in the SWCTL register, all of the logic is held in a reset state
except the master SMBus. The RSTHALT bit is only set if serial EEPROM initialization is enabled in
step 6.
8. Normal device operation begins.
A hot reset initiated by the writing of a one to the Hot Reset (HRST) bit in the Switch Control (SWCTL)
register always results in the PES4T4 returning a completion to the requester before the hot reset process
begins.
Upstream Secondary Bus Reset
An upstream secondary bus reset may be initiated by the following condition:
– A one is written to the Secondary Bus Reset (SRESET) bit in the upstream port's (i.e., port 0)
Bridge Control Register (BCTL).
2 - 7
Clock Operation
February 1, 2011
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