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Notes
PES4T4 User Manual
®
Introduction
The PES4T4 is a 4 port switch device. The upstream port link width is configured as a x1 link width and
all three downstream ports are also configured as x1 link widths.
Polarity Inversion
Each port of the PES4T4 supports automatic polarity inversion as required by the PCIe specification.
Polarity inversion is a function of the receiver and not the transmitter. The transmitter never inverts its data.
During link training, the receiver examines symbols six through sixteen of the TS1 and TS2 ordered sets for
inversion of the PExAP[n] and PExAN[n] signals. If an inversion is detected, then logic for the receiving lane
automatically inverts received data.
Polarity inversion is a lane and not a link function. Therefore, it is possible for some linked lanes to be
inverted while others are not inverted.
Link Width Negotiation
The PES4T4 supports the optional link variable width negotiation feature for its upstream port as
outlined in the PCIe specification. During link training, upstream port is capable of negotiating to a x1 link
width. The negotiated width of the upstream link may be determined from the Link Width (LW) field in the
PCI Express Link Status (PCIELSTS) register.
The Maximum Link Width (MAXLNKWDTH) field in a port's PCI Express Link Capabilities (PCIELCAP)
register contains the maximum link width of the port. This field is of RWL type in the upstream port and may
be modified when the REGUNLOCK bit is set in the SWCTL register. Modification of this field allows the
maximum link width of the port to be configured. The new link width takes effect the next time link training
occurs. To force a link width for the upstream port to a smaller width than the default value, the MAXLNK-
WDTH field could be configured through Serial EEPROM initialization and full link retraining forced.
Link Retraining
Link retraining should not cause either a downstream component or an upstream component to reset or
revert to default values.
Writing a one to the Link Retrain (LRET) bit in the upstream port's PCI Express Link Control (PCIELCTL)
register when the REGUNLOCK bit is set in the SWCTL register forces the upstream PCIe link to retrain.
When this occurs the LTSSM transitions directly to the Recovery state.
Writing a one to the Link Retrain (LRET) bit in a downstream port's PCI Express Link Control
(PCIELCTL) register regardless of the REGUNLOCK bit state in the SWCTL register forces the down-
stream PCIe link to retrain. When this occurs the LTSSM transitions directly to the Recovery state.
Writing a one to the Full Link Retrain (FLRET) bit in the Phy Link State 0 (PHYLSTSE 0) register of any
port forces that port's PCIe link to retrain. When this occurs the LTSSM transitions directly to the Detect
state.
Link Down
When a link goes down, all TLPs received by that port and queued in the switch are discarded and all
TLPs received by other ports and destined to the port whose link is down are treated as Unsupported
Requests (UR). While a downstream link is down, it is possible to perform configuration read and write
operations to the PCI-PCI bridge associated with that link. When a link comes up, flow control credits are
advertised.
Link Operation
4 - 1
Chapter 4
February 1, 2011
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