Table of Contents
Advertisement
h
0
(3) Timing chart of circuit operation
5.4.7
Reset input
M15
Shift pulse input
M26
Shift data input
Bit 10 set input
M27
Bit 23 reset input
M28
Shift output
Bit
0
M89
1
88
2
87
3
86
10
79
23
66
I!
n
I
I
A
..)--
I
I
I
I
I '
I
I
1
1
1
I
1
I
I
I
I
I
I
---I
1
I
.
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
;
]
I
I
I
I
1
1
1
I
I
I
i
n
I
I
I
I
-----I--
I
---
I
I
I
I
I
I
I
I
I
1
I
I
I
I
I
I
I
I
1
I
Forced set
I
0 0
L
t
1
-
Forced reset
Fig. 5.4.6.8 Rightward Shift Register Timing Chart
Batch shift of data register D
In order to shift contents in'data register of the standard CPU, MOV instruction must be re-
peated the same time as the number of data to be shifted and therefore a considerable number
of steps must be programmed for a large number of$ data.
When the additional function is used, the data shift may be accomplished only by specifying
head No. of data register, length of data (number of bits), and direction of shifting, thus facili-
tating programming with a short number of steps.
5.4.7.1 Functions
Function No.: F115
Head No. of register D:
Number of data registers to- be shifted:
Direction of shift:
(
leftwa rd/rig htwa rd
)
D l l O
I 0 0 5 7 1
Binary numerals
D l l l
l m ]
Binary numerals
D112
m l
loooil
Leftward
Rightward
Note: Applicable number of register range is from DO to 095. If number of registers specified
by D 1 1 1 exceeds 095, batch shift becomes impossible.
66
Advertisement
Chapters
Table of Contents
