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UG-1262
Write Upper Data Register ..................................................... 200
Lower Page Address Register .................................................. 200
Upper Page Address Register ................................................. 201
Key Register ............................................................................... 201
Write Abort Address Register ................................................ 201
Write Protection Register........................................................ 201
Signature Register ..................................................................... 202
User Configuration Register ................................................... 202
IRQ Abort Enable (Lower Bits) Register .............................. 203
IRQ Abort Enable (Upper Bits) Register .............................. 203
ECC Configuration Register ................................................... 203
ECC Status (Address) Register ............................................... 203
Analog Devices Flash Security Register ................................ 204
SRAM ............................................................................................. 205
SRAM Features ......................................................................... 205
Instruction vs. Data SRAM ..................................................... 206
SRAM Retention in Hibernate Mode .................................... 206
SRAM Initialization ................................................................. 206
Cache .............................................................................................. 208
Initialization in Cache and Instruction SRAM .................... 208
Programming Guidelines ........................................................ 208
Register Summary: Cache (FLCC_CACHE) ............................ 209
Register Details: Cache (FLCC_CACHE) ................................. 210
Cache Status Register ............................................................... 210
Cache Setup Register................................................................ 210
Cache Key Register ................................................................... 210
Silicon Identification .................................................................... 211
Register Summary: System (Digital Die) .................................. 212
Register Details: System (Digital Die) ....................................... 213
Analog Devices Identification (Digital Die) Register.......... 213
Chip Identifier (Digital Die) Register .................................... 213
Serial Wire Debug Enable Register ........................................ 213
Analog Devices Identification (Analog Die) Register ......... 213
Chip Identification (Analog Die) Register ........................... 213
Register ...................................................................................... 213
Digital Inputs and Outputs ......................................................... 214
Digital Inputs and Outputs Features ..................................... 214
Digital Inputs and Outputs Overview ................................... 214
Digital Inputs and Outputs Operation .................................. 215
Interrupts ................................................................................... 215
ADuCM355
Digital Die Port Mux ............................................................... 217
AFE Die Digital Port Mux ...................................................... 217
Register Summary: Digital Inputs and Outputs ...................... 218
Register Details: Digital Inputs and Outputs ........................... 220
GPIO Port Configuration Registers ...................................... 220
GPIO Port Output Enable Registers...................................... 220
GPIO Port Input/Output Pull-Up Enable Registers ........... 220
GPIO Port Input Path Enable Registers ............................... 221
GPIO Port Registered Data Input Registers ......................... 221
GPIO Port Data Output Registers ......................................... 221
GPIO Port Data Output Set Registers ................................... 221
GPIO Port Data Output Clear Registers ............................... 222
GPIO Port Pin Toggle Registers ............................................ 222
GPIO Port Interrupt Polarity Registers ................................ 222
GPIO Port Interrupt A Enable Registers .............................. 222
GPIO Port Interrupt B Enable Registers .............................. 223
GPIO Port Interrupt Status Registers ................................... 223
GPIO Port Drive Strength Select Registers .......................... 223
AFE GPIO Port Configuration Register ............................... 223
AFE GPIO Port Output Enable Register .............................. 224
Register ...................................................................................... 224
AFE GPIO Port Input Path Enable Register ........................ 224
AFE GPIO Port Registered Data Input ................................. 224
AFE GPIO Port Data Output Register .................................. 224
AFE GPIO Port Data Output Set Register ............................ 225
AFE GPIO Port Data Output Clear Register ....................... 225
AFE GPIO Port Pin Toggle Register ..................................... 225
2
C Serial Interface........................................................................ 226
2
C Features ............................................................................... 226
2
C Overview ............................................................................. 226
2
C Operation ............................................................................ 226
2
C Operating Modes ............................................................... 228
Master Control Register .......................................................... 232
Master Status Register ............................................................. 232
Master Receive Data Register ................................................. 233
Master Transmit Data Register .............................................. 234
Master Receive Data Count Register ..................................... 234
Master Current Receive Data Count Register ...................... 234
Rev. B | Page 6 of 312
Hardware Reference Manual
2
C ................................................................. 231
2
C ..................................................................... 232
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